Multicomputer digital processing system

• US 4,870,704 A
• Filed: 10/31/1984
• Issued: 09/26/1989
• Est. Priority Date: 10/31/1984
• Status: Expired due to Fees

• Current Assignee: Alexible Computer Corporation
• Original Assignee: Flexible Computer Corp.
• Inventors: Zsohar, Leslie, Smith, Dennis K., Leete, Thomas G., Blanchard, Michael K., Hsu, Jacob, Matelan, M. Nicholas, Naeini, Abdolreza
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Fairbanks, Jonathan C.
• Application Number:
  US06/666,991
• Time in Patent Office: 1,791 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/9, 371/10, 371/11
• US Class Current: 710/120
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 11/2023 Failover techniques
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2736 using a dedicated service processor for test
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: H01R 12/7088 Arrangements for power supply
• CPC Class Codes: H05K 7/1459 Circuit configuration, e.g. routing signals

Abstract

A multiple computer digital processing system including several Local Buses positioned orthogonally to a Common Bus. Each Local Bus is connected to the Common Bus through a plugably connected Common Bus interface card to provide a transfer of information between Local Buses across the Common Bus. Computer cards, memory cards and other device cards may be plugably connected to the Local Bus to communicate with each other via the Local Buses and Common Bus. The number and types of cards connected and even the number of Local Buses connected to the Common Bus may be varied according to the requirements of each application. Additionally, the Common Bus includes a shared memory accessible by all devices and an InterComputer Interrupt circuit providing interrupts to the computer cards. Further the computer cards are plugably connectable to a Peripheral Bus to provide communications with peripheral devices located externally to the system. All cards connected to the Local Buses and Common Bus include monitor circuits connected through a Test Bus to a System Monitor that configures the system according to the cards connected and the application requirements, detects errors, monitors performance, and provides fault tolerant repair capability under operator supervision.

Claims

1. A data processing system comprising:

A. a first bus including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a first bus protocol that defines the timing, formats for the address, data, control and interrupt information, and response format, for an information transfer between a requestor device and a responder device of a plurality of devices connected to the first bus, said control signals including;

(1) an INTERLOCK signal from said requestor to the responder defining an interlock period, wherein the responder locks out all other information transfers to it except for information transfers with the requestor until the requestor information transfer does not include the INTERLOCK control signal, during the interlock period the responder is to transmit a RETRY control signal to all devices attempting access, all devices receiving a RETRY control signal are to store an identifier code of the device sending the RETRY control signal, lock out all other access attempts responding with a RETRY control signal, monitor all information transfers on the first bus and determined if the responder'"'"'s identifier code is contained in the control signals, and upon occurrence of the code, an error indication or a timeout indication reinitiate the transfer to that responder device;

(2) a WAIT control signal from the responder in response to an access from the requestor and defining a requestor WAIT period, wherein the requestor locks out all attempted accesses responding with a RETRY control signal, monitors a plurality of control signals representing the source identifier code of the responder, responds only to access with theresponder'"'"'s source identifier code, and remains in the WAIT period until the responder has transmitted a COMPLETE control signal or until an error indication or a timeout indication;

(3) an OVERRIDE control signal defining that a device receiving the OVERRIDE control signal must relinquish control of the first bus and reinitiate its bus transaction after the transaction by the device transmitting the OVERRIDE control signal; and

(4) a TYPE control signal indicating a process wherein the transmitter of the TYPE control signal will properly respond to the INTERLOCK, RETRY, WAIT, COMPLETE and OVERRIDE control signals;

said first bus including a first plurality of serially coupled connectors along said first bus lines;

B. at least two second buses including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a second bus protocol that defines the timing formats for the addresss, data, control and interrupt information, and response format, an information transfer between a requestor and a responder device of a plurality of devices connected to the second buses, said control signal including;

(1) an INTERLOCK signal from said requestor to the responder defining an INTERLOCK period when the responder is only to respond to information transfers from the requestor until the information transfer from the requestor does not include the INTERLOCK signal or until an error indication or a timeout indication;

(2) an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal must relinquish control of the second bus and reinitiate its bus transaction after the transaction by the device sending the OVERRIDE signal; and

(3) a TYPE control signal indicating that the transmitter of the TYPE control signal will properly respond to the INTERLOCK and OVERRIDE control signals;

each of said second buses including a second plurality of connectors serially coupled to said second bus lines;

C. An input/output Bus,

D. a test bus including a plurality of lines for the serial transfer of information;

E. a plurality of computer units, each connected to one of the plurality of second buses and including;

(1) a Resource Monitor circuit connected to the test bus for controlling and monitoring the computer unit circuitry;

(2) a processor including a processor address decode means controlled by said Resource Monitor for providing addressable access to the processor for an internal bus;

(3) a computer unit clock means for providing at least one timing signal to the computer units circuitry;

(4) bus gate means for controlling the transfer of information between the internal bus, the second bus and the input/output bus;

(5) bus address decode means for decoding addresses from either the second bus or the input/output bus, and indicating when the address is within an address space provided by the Resource Monitor;

(6) an interrupt handler for receiving interrupts from the second or input/output buses and accordingly generating signals to the processor;

(7) a bus requestor for receiving requests for access to either the second or the input/output bus and interfacing with an arbiter circuit provided to generate bus access grants in accordance with an arbitration scheme from the Resource Monitor;

(8) access control means for controlling the transfer of information between the internal bus, the input/output bus, the processor, a memory, and the second bus by (a) generating enabling signals to enable transfer of information from either the second or input/output bus, the processor or the memory along the internal bus, (b) providing an appropriate response to transfers received from either the input/output bus or the second bus, (c) providing the appropriate signals to either the input/output bus or the second bus for a transfer of information from said processor, and (d) providing the appropriate signals for a transfer of information from either the second or input/output bus to the other;

F. a first bus control unit connected to the first bus and a unique one of the plurality of second buses and;

G. at least one first bus access unit connected to the first bus and each connected to a unique one of the remaining second buses;

said first bus control unit and first bus access unit each including;

(1) a bus requestor for transmitting a request for access to either the first or second bus and receiving access grants in response thereto;

(2) a bus address decode means for decoding addresses on either bus and indicating a transfer between buses;

(3) bus information interface means for transferring information from one bus to the other in response to control signals;

(4) protocol logic for (a) receiving address indications, (b) transmitting access requests in response thereto, (c) generating control signals to provide an information transfer (d) generating a response to the received address transfer;

(5) a unit Resource Monitor for controlling and monitoring the unit circuitry and connected to the Test Bus;

(6) a common lock interface for providing data to either bus, said data including the accessibility status of system addressable devices and for transmitting requests to access the devices;

(7) second bus arbiter for receiving second bus access requests and for providing grants for access to the second bus;

(8) an interrupt interface means connected to receive a time division multiplexed interrupt signal from the first bus and generate an interrupt to a computer unit on the second bus;

said first bus control unit further including;

(1) bus request arbitration logic means for receiving first bus access requests and providing first bus grants;

(2) a common lock arbitration means for receiving requests to access system addressable devices and for granting these requests in accordance with a device access arbitration scheme;

(3) InterComputer interupt control logic connected to the first bus and including (a) interrupt address decode means for indicating that a first bus information transfer is an interrupt control logic access, (b) an interrupt word register for storing of interrupt status information for each computer unit, the status accessible to first bus information transfers, (c) interrupt generation means to generate a time division multiplexed signal including an interrupt to a computer unit when its respective word register receives data from an information transfer, and (d) interrupt response logic for generating appropriate protocol responses to information transfers to the interrupt control logic unit;

said first bus access unit further including a memory connected to the first bus for responding to information transfers addressed thereto;

H. a system monitor including processing means connected to the Test Bus for monitoring and controlling system operation and further including a mass memory device for the storage of system configuration information and system monitoring information, and a network interface connectable to other system monitor units of other data processing systems.

2. A data processing system comprising:

A. a Common Bus including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a Common Bus protocol that defines the timing and formats for the address, data, control and interrupt information, and response, for an information transfer between a requestor device and a responder device of a plurality of devices connected to the Common Bus, said control information including;

(1) an INTERLOCK signal from said requestor to the responder defining an interlock period, wherein the responder locks out all other information transfers to it except for information transfers with the requestor until the requestor information transfer does not include the INTERLOCK control signal, during the interlock period the responder is to transmit a RETRY control signal to all devices attempting access, all devices receiving a RETRY control signal are to store an identifier code of the device sending the RETRY control signal, lock out all other access attempts responding with a RETRY control signal, monitor all information transfers on the Common Bus and determine if the responder'"'"'s identifier code is contained in the control signals, and upon occurrence of the code, an error indication or a timeout indication reinitiate the transfer to that responder device;

(2) a WAIT control signal from the responder is response to an access from the requestor and defining a requestor WAIT period, wherein the requestor locks out all attempted accesses responding with a RETRY control signal, monitors a plurality of control signals representing the source identifier code of the responder, responds only to accesses with the responder'"'"'s source identifier code, and remains in the WAIT period until the responder has transmitted a COMPLETE control signal or until an error indication or a timeout indication;

(3) an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal must relinquish control of the Common Bus and reinitiate its bus transaction after the transaction by the device transmitting the OVERRIDE control signal; and

(4) a TYPE control signal indicating that the transmitter of the TYPE control signal will properly respond to the INTERLOCK, RETRY, WAIT, COMPLETE and OVERRIDE control signals.

said Common Bus including a first plurality of serially coupled connectors along said Common Bus lines;

B. at least two Local Buses including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a Local Bus protocol that defines the timing, formats for the address, data, control and interrupt information, and response format, and information transfer between a requestor and a responder device of a plurality of devices connected to the Local Buses, said control signals including;

(1) an INTERLOCK signal from said requestor to the responder defining an INTERLOCK period when the responder is only to respond to information transfers from the requestor until the information transfer from the requestor does not include the INTERLOCK signal or until an error indication or a timeout indication;

(2) an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal must relinquish control of the Local Bus and reinitiate its bus transaction after the transaction by the device sending the OVERRIDE signal; and

(3) a TYPE control signal indicating that the transmitter of the TYPE control signal with properly respond to the INTERLOCK and OVERRIDE control signals;

each of said Local Buses including a second plurality of connector serially coupled to said Local Bus lines;

C. a Peripheral Bus including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a protocol similar to the Local Bus protocol;

D. a Test Bus including a plurality of lines for the serial transfer of information, said Test Bus serially connected to a selected plurality of said Local Bus connectors;

E. each of said Local Bus connectors positioned to receive a computer unit including;

(1) a Resource Monitor circuit connected to the Test Bus for controlling said monitoring the computer unit circuitry;

(2) a processor for independently executing instructions on data and connected to the Resource Monitor and a computer unit Internal Bus and further including an address decode circuit for receiving a processor address space from the Resource Monitor and for providing a signal to the processor when an address present on the Internal Bus is within the processor address space;

(3) a computer unit clock means for providing at least one timing signal to the computer unit circuitry;

(4) bus gate means for controlling the transfer of information between the Peripheral Bus and Local Bus and a computer unit Internal Bus;

(5) bus address decode means for receiving address information from either said Local Bus or Peripheral Bus, comparing the address with a computer unit address space provided from said Resource Monitor, determining when the address is within the address space, accordingly, generating an address decode signal;

(6) an Internal Bus gate means connected to the Local Bus and Peripheral Bus for controlling the transfer of information to an Internal Bus;

(7) an interrupt handler for receiving interrupt signals from either the Peripheral Bus or the Local Bus and generating signals to the processor indicating the reception of the interrupt, and generating response signals for transmission on the Peripheral Bus or Local bus indicating acknowledgement of the receipt of the interrupt;

(8) a bus requestor and arbiter means for receiving signals from said processor or one of the buses indicating a request for access to the other bus and for receiving signals from the Resource Monitor designating which one of a plurality of arbitration lines to transmit the request and further including an arbitration circuit for receiving request signals from the arbitration lines and for generating a signal indicating a grant of bus access on one of the arbitration lines, said Resource monitor controlling the operation of the arbiter means and controlling which of a plurality of arbitration schemes within the arbitration means determines which of the received requests is granted bus access;

(9) access control means for providing a plurality of control signals to regulate the transfer of information between the processor, a memory, the Local Bus and the Peripheral Bus and including;

(a) bus control signal circuitry means (i) and (A) receiving a plurality of control signals from either the processor or one bus representing a request for generating an information transfer on the other bus, (B) transmitting the request to the other bus requestor, (C) generating signals for an information transfer on the other bus in accordance with bus protocol, (d) generating control signals to the other bus gate means for transferring the information to the other bus upon the receipt of the grant, or, (ii) in response to information on the other bus, (A) generating control signals to the other bus gate means and Internal Bus gate means for receiving information from the other bus, (B) receiving the indication from the other bus address decode means and, (C) in accordance with such indication, (I) generating a plurality of synchronization signals to either the processor or the memory for the reception of information from said bus, or (II) for (a) generating control signals to initiate bus transfer from other bus to the bus gate means for the transfer of information from the other bus, (b) transmitting a request for access to the one bus requestor;

(c) generating a response on the other bus to respond to the received information and (d) generating control signals to the one bus buffer for gating the information, in accordance with an access grant;

(b) an Internal Bus control means for regulating the information flow on the Internal Bus by controlling access to the Internal Bus by the processor, the memory, the Peripheral Bus and the Local Bus and including an internal arbiter for receiving Internal Bus request signals from the processor, the bus address decoder, the interrupt handler, and the bus requestor, and for generating an Internal Bus grant signal in accordance with a predetermined arbitration scheme, and providing enabling signals to Internal Bus gate logic for an information transfer over the Internal Bus;

F. a Common Bus control unit connected to the Common Bus and a unique one of the plurality of Local Buses and;

G. at least one Common Bus access unit connected to the Common Bus and each connected to a unique one of the remaining Local Buses;

said Common Bus control unit and Common Bus access unit each including;

(1) a Common Bus buffer means for gating the transfer of information between the Common Bus and a unit Internal Common Bus in accordance with received control signals;

(2) a Local Bus buffer means for gating information between the Local Bus and the buffered Local Bus in accordance with received control signals;

(3) a Common Bus requestor means for receiving a request for Common Bus access and for transmitting the request on one of a plurality of request lines, said lines selected by a unit Resource Monitor, and for receiving a grant indication upon the selected line;

(4) a Common Bus address decode means for receiving Common bus signals including a Common Bus address, comparing the received Common Bus address with a Local Bus address space provided from the unit Resource Monitor, determining when the Common Bus address is within the Local Bus address space and, accordingly, generating a signal indicating that the information present on the Common Bus is to be transferred to the connected Local Bus;

(5) a Local Bus to Common Bus address decode means for receiving Local Bus signals including a Local Bus address, comprising the received local Bus address with a Common Bus address space provided by the Resource Monitor, determining when the Local bus address is within the Common Bus address space and, accordingly, generating a signal indicating the information present on the connected Local Buses is to be transferred to the Common Bus;

(6) Common Bus/Local Bus interface means for latching information for transfer from the Internal Common Bus to the buffered Local Bus and for gating information from the buffered Local Bus to Common Bus in accordance with received control signals;

(7) a Local Bus requestor and arbiter for receiving signals indicating an access request Local Bus, transmitting the request to a connected arbitration circuit for generating a signal indicating a grant of Local Bus access, said Resource Monitor controlling the operation of the arbitration circuit by indicating which one of the plurality of arbitration schemes within the arbitration circuit determines which one of the received requests is granted Local Bus access;

(8) protocol signal control logic means for, (A) in response to information on the connected Local Bus;

(1) generating control signals to the Local Bus buffer means for receiving information onto the buffered Local Bus;

(2) receiving said decode indication and, in accordance therewith;

(3) transmitting a request for Common Bus access,

(4) generating control signals to the Common Bus/Local Bus interface to transfer information;

(5) generating a response to the Local Bus;

(6) generating control signals to the Common Bus buffer for gating the information on the Internal Common Bus to the Common Bus in accordance with a grant;

and for, (B) in response to information on the Common Bus,

(1) generating control signals to the Common Bus buffer means for receiving information onto the Internal Common Bus;

(2) receiving said decode indication and, in accordance therewith;

(3) transmitting a request for Local Bus access;

(4) generating control signals to the Common Bus/Local Bus interface means to latch information;

(5) generating a response to the Common Bus;

(6) generating control signals to the Local Bus buffer for gating the information on the buffered Local Bus to the Local Bus in accordance with a grant signal form the Local Bus requestor;

(9) a unit Resource Monitor including means for controlling and monitoring unit circuitry and connected to the Test Bus;

(10) a unit clock means for providing at least one timing signal to the Common Bus control unit circuitry;

(11) common lock interface means connected to the buffered Local Bus for responding to the addresses specified by the Resource Monitor and providing status information of individual system addressable devices and further connected to a Lock Bus for transmitting requests for access to the individual system addressable devices and for receiving grants of such requests;

(12) an InterComputer interrupt interface means connected to the common Bus and the Local Bus for receiving a time division multiplexed interrupt signal, and including circuitry that receives inputs from the Resource Monitor for demultiplexing the interrupt signal and generating an InterComputer interrupt signal on the Local Bus in response thereto;

said Common Bus control unit further including;

(1) common lock arbitration means connected to the Lock Bus for receiving said requests and for providing grants to access the individual system addressable device in accordance with information from the Resource Monitor;

(2) Common Bus request arbitration logic means connected to receive requests for access to the Common Bus and for granting Common Bus requests in accordance with information from the Common Bus control unit Resource Monitor;

(13) Intercomputer interrupt control logic connected to the Internal Common Bus and including;

(a) interrupt control address decode means to receive address information from the Common Bus, comparing the received address with an InterComputer interrupt control address space provided by the Resource Monitor, determining when the received address is within the address space, and accordingly generating a signal indicating the information present on the Common Bus is to be received by the InterComputer interrupt control logic;

(b) interrupt word register means for receiving said indication signal and selecting one of a plurality of registers in accordance with said received address, and either, ORing the contents of the selected register with the Common Bus data and storing the ORed results in the register for a write operation, or clearing the contents of the register after a read operation;

(c) interrupt generation means for receiving said indication signal from the InterComputer interrupt decoder means, and, for a write operation, generating at time division multiplex signal including an interrupt in accordance with the received address, and transmitting the time division multiplexed interrupt signal on the Common Bus;

(d) InterComputer interrupt response logic means to generate response signals to the received Common Bus address, in accordance with the Common Bus protocol;

said Common Bus access unit further including;

(14) Common bus memory circuit including;

(a) Common Bus memory address decode means for receiving Common bus signals including a Common Bus address, comparing the received Common Bus address with a Common Bus memory address space provided by the Resource Monitor determining, when the received Common Bus address is within the Common Bus memory address space, and, accordingly generating a signal indicating that the information on the Common bus is to be transferred to the Common Bus memory;

(b) Common Bus memory interface logic means for receiving the indicating signal, generating access signals to the Common Bus memory for providing access to the Common Bus memory in accordance with the Common Bus address, data and control signals;

(c) Common Bus memory response logic means for generating a response on the Internal Common Bus to the Common Bus information and generating control signals to the Common Bus buffer for the transfer of the response from the Internal Common bus to the Common Bus;

H. a system monitor means including a first processor for transferring information via the Test bus to the Resource Monitors of the computer units, Common Bus access units and Common Bus control unit and connected to at least one environmental sensor, a first address specification device, a real time clock, a power relay for controlling power to the data processing system, a mass memory for storing program information including the configuration information for each Common Bus control unit, Common Bus access unit, and computer unit, and a first processor memory means for storing a program of instructions for execution by the first processor for (1) the transfer of the configuration information by the Test Bus to each Resource Monitor, (2) for monitoring the system operation from the Resource Monitors, (3) for receiving information from and providing information to an operator terminal, (4) for regulating power to the data processing system through the power relay in accordance with information received from the environmental sensor, said first processor connected to first and second data buffers, said data buffers further connected to a second processor, said first data buffer providing storage of data from said first processor to said second processor and said second data buffer providing storage of data from said second processor to said first processor, said second processor connected to a second address specification device, a network bus, and a second processor memory which includes instructions for execution by said second processor to provide;

(1) transfer of information with said first processor via the first and second data buffers and (2) transfer of information via the network bus.

3. A data processing system comprising:

A. a Common Bus including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a Common Bus protocol that defines the timing and formats for the address, data, control and interrupt information, and response format, for an information transfer between a requestor device and a responder device of a plurality of devices connected to the Common Bus, said control information including;

(1) an INTERLOCK signal from said requestor to the responder defining an interlock period, wherein the responder locks out all other information transfers to it except for information transfers with the requestor until the requestor information transfer does not include the INTERLOCK control signal, during the interlock period the responder is to transmit a RETRY control signal to all devices attempting access, all devices receiving the RETRY control signal are to store an identifier code of the device sending the RETRY control signal, lock out all other access attempts responding with a RETRY control signal, monitor all information transfers on the Common Bus and determine if the responder'"'"'s identifier code is contained in the control signals, and upon occurrence of the code, an error indication or timeout indication reinitiates the transfer to that responder device;

(2) a WAIT control signal from the responder in response to an access from the requestor and defining a requestor WAIT period, wherein the requestor locks out all attempted accesses responding with a RETRY control signal, monitors a plurality of control signals representing the source identifier code of the responder, responds only to accesses with the responder'"'"'s source identifier code, and remains in the WAIT period until the responder has transmitted a COMPLETE control signal or until an error indication or a timeout indication;

(3) an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal must relinquish control of the Common bus and reinitiate its bus transaction after the transaction by the device transmitting the OVERRIDE control signal; and

(4) a TYPE control signal indicating that the transmitter of the TYPE control signal will propelly respond to the INTERLOCK, RETRY, WAIT COMPLETE and OVERRIDE control signals;

said Common bus including a first plurality of serially coupled connectors along said Common Bus lines;

B. at least two Local Buses including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with a Local bus protocol that defines the timing and formats for the address, data, control and interrupt information, and response format, an information transfer between a requestor and a responder device of a plurality of devices connected to the Local Buses, said control signals including;

(1) an INTERLOCK signal from said requestor to the responder defining an INTERLOCK period when the responder is only to respond to information transfers from the requestor until the information transfers from the requestor does not include the INTERLOCK signal or until an error indication or a timeout indication;

(2) an OVERRIDE control signal defining a process wherein a device receiving the OVERRIDE control signal must relinquish control of the Local Bus and reinitiate its bus transaction after the transaction by the device sending the OVERRIDE signal; and

(3) a TYPE control signal indicating that the transmitter of the TYPE control signal will properly respond to the INTERLOCK and OVERRIDE control signals;

each of said Local Buses including a second plurality of connectors serially coupled to said Local Bus lines, and said Local Bus positioned approximately orthogonally to said Common Bus lines;

C. a Peripheral Bus including a plurality of signal lines for the transfer of power and address, data, control and interrupt information in accordance with the Local Bus protocol;

D. a Test Bus including a plurality of lines for the serial transfer of information, said Test Bus serially connected to a selected plurality of said Local bus connectors;

E. each of said Local Bus connectors positioned to receive a computer unit including;

(1) a Resource Monitor circuit connected to the Test Bus for controlling and monitoring the computer unit circuitry;

(2) a processor for independently executing instructions on data and connected to the Resource Monitor and a computer unit Internal Bus and further including an address decode circuit for receiving a processor address space from the Resource Monitor and for providing a signal to the processor when an address present on the Internal Bus is within the processor address space;

(3) a computer unit clock means for providing at least one timing signal to the computer unit circuitry;

(4) Peripheral Bus gate means for controlling the transfer of information between the Peripheral Bus and a computer unit Internal Peripheral Bus;

(5) a Local Bus gate means for controlling the transfer of information between the Local Bus and a computer unit Internal Local Bus;

(6) a Peripheral Bus address decoding circuit means for receiving Peripheral Bus signals including a Peripheral Bus address, comparing the received Peripheral Bus address with a computer unit Peripheral Bus address space and when the Peripheral Bus address is within the address space, generating a signal indication that the information present on the Peripheral Bus is to be transferred to the Internal Bus, said Peripheral Bus decoding means including circuitry connected to receive the address space from the Resource Monitor;

(7) a Local Bus address decoding circuit means for receiving Local Bus signals including a Local Bus address, comparing the received Local Bus address with a computer unit Local bus address space and when the Local Bus address is within the address space, generating a signal indicating that the information present on the Local Bus is to be transferred to the Internal Bus, said Local Bus decoding means including circuitry connected to receive the address space from the Resource Monitor;

(8) a Peripheral Bus interface means connected to the Internal Local Bus and the Internal Peripheral Bus for storing address translation information provided from the Resource Monitor and for providing a translated address to the Internal Local Bus in response to an address present on the Internal Peripheral Bus;

(9) an Internal Bus gate means connected to the Internal Local Bus, the Internal Peripheral Bus through the Peripheral Bus address interface means and the Internal Bus, for controlling the transfer of information from either the Internal Local Bus or the Internal Peripheral Bus to the Internal Bus;

(10) an interrupt handler for receiving interrupt signals from either the Peripheral Bus or the Local Bus and generating signals to the processor indicating the reception of the interrupt, and generating response signals for transmission indicating acknowledgement of the receipt of the interrupt;

(11) a Local Bus requestor and arbiter means for receiving signals form said processor or the Peripheral Bus indicating a request for access to the Local Bus and for receiving signals from the Resource Monitor designating which one of a plurality of arbitration lines to transmit the request and further including an arbitration circuit for receiving request signals from the arbitration lines and for generating a signal indicating a grant of Local Bus access on one of the arbitration lines, said Resource Monitor controlling the operation of the arbitration circuit controlling which of a plurality of arbitration schemes within the arbitration means determines which of the received requests is granted Local Bus access;

(12) a Peripheral Bus requestor and arbiter means for receiving signals from said processor of said Local Bus indicating a request for access to the Peripheral Bus and for receiving signals from the Resource monitor designating which one of a plurality of arbitration lines to transmit the request and further including an arbitration circuit for receiving request signals from the arbitration lines and for generating a signal indicating a grant of Peripheral Bus access on one of the arbitration lines, said Resource Monitor controlling the operation of the arbitration circuit and controlling which of a plurality of arbitration schemes within the arbitration circuit determines which one of the received requests is granted a Peripheral Bus access;

(13) access control means for providing a plurality of control signals to regulate the transfer of information between the processor, a memory, the Local Bus and the Peripheral Bus and including;

(a) Peripheral Bus control signal circuitry means (i) for (A) receiving a plurality of control signals from either the processor representing a request for generating an information transfer on the peripheral Bus, (B) transmitting the request to the Peripheral Bus requestor, (C) generating signals for an information transfer on the Peripheral Bus in accordance with Peripheral Bus protocol, (D) generating control signals to the Peripheral Bus gate means for transferring the information to the Peripheral Bus upon the receipt of the Peripheral Bus grant from the Peripheral Bus requestor and arbiter means and, (ii) in response to information on the Peripheral bus, (A) generating control signals to the Peripheral Bus gate means and Internal Bus gate means for receiving information from the Peripheral Bus, (B) receiving the indication signal from the Peripheral Bus address decode circuit means and, (C) in accordance with such indication signal, (I) generating a plurality of synchronization signals to either the processor or the memory for the reception of information from said Peripheral Bus, or (II) for (a) generating control signals to initiate a Local Bus transfer and to the Local Bus gate means for the transfer of information from the Peripheral Bus to the Local Bus, (b) transmitting a request for access to the Local Bus to the Local bus requestor, (c) generating a response on the Peripheral Bus to respond to the received Peripheral Bus information and to the Peripheral Bus gate means to enable the transfer of the response information, and (d) generating control signals to the Local Bus buffer for gating the information to the Local bus, in accordance with a grant from the Local Bus requestor,

(b) Local bus control signal circuitry means (i) for (A) receiving a plurality of control signals from the processor representing a request for generating an information transfer on the Local Bus, (B) transmitting the request to the Local bus requestor, (C) generating signals for an information transfer on the Local Bus in accordance with Local bus protocol, (D) generating control signals to the Local Bus gate means for transferring the information to the Local bus upon the receipt of the Local Bus grant from the Local Bus requestor and arbiter means or, (ii) in response to information on the Local Bus, (a) generating control signals to the Local Bus gate means and Internal Bus gate means for receiving information from the Local Bus, (B) receiving the indication from the Local Bus address decode circuit means and, (C) in accordance with such indication, (I) generating a plurality of synchronization signals to either the processor or the memory for the reception of information from said Local Bus, or (II) for (a) generating control signals to initiate a Peripheral Bus transfer and generating control signals to the Peripheral Bus gate means for the transfer of information from the Local Bus to the Peripheral Bus, (b) transmitting a request for access to the Peripheral Bus to the Peripheral Bus requestor, (c) generating a response on the Local bus to respond to the received Local Bus information and to the Local Bus gate means to enable the transfer of the response information, and (d) generating control signals to the Peripheral Bus buffer for gating the information to the Peripheral Bus in accordance with a grant from the Peripheral Bus requestor;

(c) an Internal Bus control means for regulating the information flow on the Internal Bus by controlling access to the Internal Bus by the processor, the memory, the Internal Peripheral Bus and the Internal Local Bus and including an internal arbiter for receiving Internal Bus request signals from the processor, the Local Bus address decoder, the Peripheral Bus address decoder, the interrupt handler, the Local bus requestor and the Peripheral bus requestor, and for generating an Internal Bus access grant in accordance with a predetermined arbitration scheme, and providing enabling signals to Internal Bus gate logic for an information transfer over the Internal Bus;

(14) address processing circuit means for providing an address interface between the processor and the Internal Bus and including an address extension means initialized by the Resource monitor, and connected to the Internal Bus and the processor for providing a plurality of noncontiguous address spaces for the processor, and an address modifier means initialized by the Resource monitor, for providing additional address information for either the Peripheral Bus or Local Bus; and

(15) the memory for storage of information and connected to the Internal Bus and a memory control means, the memory control means connected to receive control signals from the access control means for enabling information to be read from and written to the memory via the Internal Bus, said memory control means further generating an access to the memory upon every operations cycle and completing the access if memory is being accessed via the Internal bus or providing a refresh signal to the memory if the memory is not being accessed by the Internal Bus;

F. a Common Bus control unit connected to the Common bus and a unique one of the plurality of Local Buses and including;

(1) a Common Bus buffer means for gating the transfer of information between the Common Bus and a unit Internal Common Bus in accordance with received control signals;

(2) a Local Bus buffer means for gating information between the Local Bus and the buffered Local Bus in accordance with received control signals;

(3) a Common bus requestor means for receiving a signal indicating a request for access to the Common Bus and for transmitting the request on one of a plurality of request lines, said line selected by a Common bus control unit Resource Monitor, and for receiving an access grant indication signal upon the selected line;

(4) a Common bus to Local Bus address decode means for receiving Common Bus signals including a Common Bus address, comparing the received Common Bus address with a Local Bus address space, determining when the common bus address is within the Local Bus address space, and accordingly, generating a signal indicating that the information present on the Common Bus is to be transferred to the connected Local Bus, said decoding means including circuitry connected to receive the Local Bus address space from the Resource Monitor;

(5) a Local Bus to Common Bus address decode means for receiving Local Bus signals including a Local Bus address, comparing the received Local Bus address with a Common bus address space, determining when the Local Bus address is within the Common bus address space and, accordingly, generating a signal indicating the information present on the connected Local Buses is to be transferred to the Common Bus, said decoding means including circuitry connected to receive the Common bus address space from the Resource monitor;

(6) Common Bus/Local Bus interface means for latching information for transfer from the Internal Common Bus to the buffered Local Bus and for gating information from the buffered Local Bus to Common Bus in accordance with received control signals;

(7) a Local Bus requestor and arbiter for receiving signals indicating a request for access to the connected Local Bus and for receiving signals from the Common Bus control unit Resource Monitor designating which one of a plurality of arbitration lines to transmit the request and further including an arbitration circuit for receiving request signals from the arbitration lines and for generating a signal indicating a grant of Local Bus access on one of the arbitration lines, said Resource Monitor controlling the operation of the arbitration circuit by indicating which one of the plurality of arbitration schemes within the arbitration circuit determines which one of the received requests is granted Local Bus access;

(8) protocol signals control logic means for, (A) in response to information on the connected Local Bus,

(1) generating control signals to the Local Bus buffer means for receiving information onto the buffered Local Bus,

(2) receiving said indication signal from the Local Bus to Common Bus address decode means and, in accordance with such indication,

(3) transmitting a request for Common bus access to the Common Bus requestor means,

(4) generating control signals to the Common Bus/Local Bus interface means for transferring information from the buffered Local Bus to the Internal Common Bus,

(5) generating a response on the buffered Local Bus and generating control signals to the Local Bus buffer for transfer of the response from the buffered Local Bus to the Local Bus,

(6) generating control signals to the Common Bus buffer for gating the information on the Internal Common bus to the Common Bus in accordance with a grant signal from the Common Bus requestor;

or, (B) in response to information on the Common Bus,

(1) generating control signals to the Common Bus buffer means for receiving information onto the Internal Common Bus;

(2) receiving said indication from the Common Bus to Local Bus address decode means and in accordance with such indication;

(3) transmitting a request for Local Bus access to the Local Bus requestor means;

(4) generating control signals to the Common Bus/Local Bus interface means for latching information from the Internal Common Bus to the buffered Local Bus;

(5) generating a response on the Internal Common Bus and generating control signals to the Common Bus buffer for the transfer of the response from the Internal Common bus to the Common bus;

(6) generating control signals to the Local Bus buffer for gating the information on the buffered Local Bus to the Local Bus in accordance with a grant signal from the Local Bus requestor;

(9) the Common Bus control unit Resource Monitor including means for controlling and monitoring the Common Bus control unit circuitry and connected to the Test bus;

(10) Common bus control unit clock means for providing at least one timing signal to the Common Bus control unit circuitry;

(11) common lock interface means connected to the buffered Local Bus for responding to addresses specified by the Resource Monitor, providing status information of individual system addressable devices, and further connected to a Lock Bus for transmitting requests for access to the individual system addressable devices and for receiving grants to such requests;

(12) common lock arbitration means connected to the Lock Bus for receiving said requests and for providing grants to access the individual system addressable devices in accordance with information from the Resource Monitor;

(13) Common Bus request arbitration logic means connected to receive requests for access to the Common Bus and for granting Common Bus requests in accordance with information from the Common Bus control unit Resource Monitor;

(14) InterComputer interrupt control logic connected to the Internal Common Bus and including;

(a) interrupt control address decode means to receive address information from the Common Bus, comparing the received address with an InterComputer interrupt control address space provided by the Resource Monitor for determining when the received address is within the address space, and accordingly generating a signal indicating that information present on the Common Bus is to be received by the InterComputer interrupt control logic;

(b) interrupt word register means for receiving said indication signal and selecting one of a plurality of registers in accordance with said received address, and either, ORing the contents of the selected register with the Common Bus data and storing the ORed results in the register for a write operation, or clearing the contents of the register after a read operation;

(c) interrupt generation means for receiving said indication signal from the InterComputer interrupt decoder means, and, for a write operation, generating a time division multiplex signal including an interrupt signal in accordance with the received address, and transmitting the time division multiplexed interrupt signal on the Common Bus;

(d) InterComputer interrupt response logic means to generate response signals to the received Common Bus address, in accordance with the Common bus protocol;

(15) an InterComputer interrupt interface means connected to the Common Bus and the Local Bus for receiving a time division multiplexed interrupt signal, and including circuitry that receives inputs from the Resource Monitor for demultiplexing the interrupt signal and generating an InterComputer interrupt signal on the Local bus to a designated computer unit in response thereto;

G. at least one Common Bus access unit connected to the Common Bus and each connected to a unique one of the remaining plurality of Local Buses and including;

(1) a Common bus buffer means for gating the transfer of information between the Common Bus and a unit Internal Common Bus in accordance with received control signals;

(2) a Local Bus buffer means for gating information between the Local Bus and the buffered Local Bus in accordance with received control signals;

(3) a Common bus requestor means for receiving a signal indicating a request for access to the Common bus and for transmitting the request on one of a plurality of request lines, said lines selected by a Common Bus access unit Resource Monitor, and for receiving a grant indication upon the selected line;

(4) a Common bus to Local Bus address decode means for receiving Common Bus signals including a Common Bus address, comparing the received Common Bus address with a Local Bus address space, determining when the Common Bus address is within the Local Bus address space and, accordingly, generating a signal indicating that the information present on the Common bus is to be transferred to the connected Local Bus, said decoding means including circuitry connected to receive the Local Bus address space from the Resource Monitor;

(5) a Local Bus to Common Bus address decode means for receiving Local Bus signals including a Local Bus a -dress, comparing the received Local Bus address with a Common Bus address space, determining when the Local Bus address is within the Common bus address space and accordingly generating a signal indicating the information present on the connected Local Buses is to be transferred to the Common Bus, said decoding means including circuitry connected to receive the Common Bus address space from the Resource Monitor;

(6) Common Bus/Local Bus interface means for latching information for transfer from the Common Bus to the Buffered Local bus and for gating information from the buffered Local Bus to Common Bus in accordance with received control signals;

(7) a Local Bus requestor and arbiter for receiving signals indicating a request for access to the connected Local bus and for receiving signals from the Common Bus access unit Resource Monitor designating which one of a plurality of arbitration lines to transmit the request and further including an arbitration circuit for receiving request signals from the arbitration lines and for generating a signal indicating a grant of Local Bus access on one of the arbitration lines, said Resource Monitor controlling the operation of the arbitration circuit by indicating which one of the plurality of arbitration schemes within the arbitration circuit determines which one of the received requests is granted Local Bus access;

(8) protocol signal control logic means for, (A) in response to information on the connected Local Bus;

(1) generating control signals to the Local Bus buffer means for receiving information onto the buffered Local Bus;

(2) receiving said indication from the Local Bus to Common bus address decode means and in accordance with such indication;

(3) transmitting a request for Common Bus access to the Common Bus requestor means;

(4) generating control signals to the Common Bus/Local Bus interface means for transferring information from the buffered Local Bus to the Internal Common Bus;

(5) generating a response on the buffered Local Bus and generating control signals to the Local Bus buffer for transfer of the response from the buffered Local Bus to the Local Bus;

(6) generating control signals to the Common bus buffer for gating the information on the Internal Common bus to the Common Bus in accordance with a grant signal from the Common bus requestor;

or, (B) in response to information on the Common Bus,

(1) generating control signals to the Common Bus buffer means for receiving information onto the Common Bus;

(2) receiving said indication from the Common Bus to Local Bus address decode means and in accordance with such indication;

(3) transmitting a request for Local Bus access to the Local bus requestor means;

(4) generating to the Common Bus/Local Bus interface means for latching information from the Internal Common bus to the buffered Local Bus;

(5) generating a response on the Internal Common Bus and generating control signals to the Common Bus buffer for the transfer of the response from the Internal Common Bus to the Common Bus;

(6) generating control signals to the Local Bus buffer for gating the information on the buffered Local Bus to the Local bus in accordance with a grant signal from the Local Bus requestor;

(9) the Common Bus access unit Resource Monitor including means for controlling and monitoring the Common Bus control unit circuitry and connected to the Test Bus;

(10) Common Bus control unit clock means for providing at least one timing signal to the Common Bus control unit circuitry;

(11) common lock interface means connected to the buffered Local Bus for responding to addresses specified by the Resource Monitor, providing status information of individual system addressable devices, and further connected to a Lock bus for transmitting requests for access to the individual system addressable devices and for receiving grants to such requests;

(12) an InterComputer interrupt interface means connected to the Common bus and the Local Bus for receiving a time division multiplexed interrupt signal, and including circuitry that receives inputs from the Resource Monitor, said circuitry for demultiplexing the interrupt signal and generating an InterComputer interrupt signal on the Local Bus in response thereto;

(13) a Common Bus memory circuit including;

(a) Common Bus memory address decode means for receiving Common bus signals including a Common Bus address, comparing the received Common Bus address with a Common Bus memory address space provided by the Resource Monitor, determining when the received Common Bus address is within the Common Bus memory address space, and accordingly, generating a signal indicating that the information on the Common Bus is to be transferred to the Common Bus memory;

(b) Common Bus memory interface logic means for receiving the indicating signal, generating access signals to the Common Bus memory for providing access to the Common Bus memory in accordance with the Common Bus address, data and control signals;

(c) Common Bus memory response logic means for generating a response on the Internal Common Bus to the Common Bus information and generating control signals to the Common Bus buffer for the transfer of the response from the Internal Common Bus to the Common Bus; and

H. a system monitor means including a first processor for transferring information via the Test Bus to the Resource Monitors of the computer units, Common Bus access units and Common Bus control unit and connected to at least one environmental sensor, a first address specification device, a real time clock, a power relay for controlling power to the data processing system, a mass memory for storing program information including the configuration information for each Common Bus control unit, Common Bus access unit, and computer unit, and a first processor memory means for storing a program of instructions for execution by the first processor for;

(1) the transfer of the configuration information by the Test Bus to each Resource Monitor, (2) for monitoring the system operation from the Resource Monitors, (3) for receiving information from and providing information to an operator terminal, (4) for regulating power to the data processing system through the power relay in accordance with information received from the environmental sensor, said first processor connected to first and second data buffers, said data buffers further connected to a second processor, said first data buffer providing storage of data from said first processor to said second processor and said second data buffer providing storage of data from said second processor to said first processor, said second processor connected to a second address specification device, a network bus, and a second processor memory which includes instructions for execution by said second processor to provide;

(1) transfer of information with said first processor via the first and second data buffers and (2) transfer of information via the network bus.

4. A data processing apparatus comprising:

a plurality of comptuer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;

said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;

said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and

said shared memory means including a memory having a plurality of segments corresponding to the addresses of the plurality of connector means;

said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means ina a desired arbitrating order, means for defining a common bus access cycle, means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or devices resident on the common bus, said signal representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding ones of the linked plurality of interface means in arbitration of the access requests;

said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means;

wherein the plurality of computer means protocols further include;

means responsive to an access request for sending a wait signal when a response will take longer than one bus cycle, means responsive to a wait signal for entering a state wherein the computer means is accessible only by a device sending the received wait signal, means for sending a retry signal to any other device requesting access during the wait state, means responsive to receipt of a retry signal for identifying the retry sending device and means for reintiating an access request to the retry sending device; and

each protocol means of the intercomputer interrupt means including means for issuing an override signal to a local bus device sending an access signal while the common bus is attempting to access the local bus device for resolving bus contentions between the common bus and local bus device in favor or the one having the faster transfer rate.

5. A data processing apparatus comprising:

a plurality of computer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;

said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;

said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and

said shared memory means including a memory having a plurality of segments corresponding to the addresses of the plurality of connector means and further includes a programmable decoder means for detecting when access to the common bus is required, said programmable decoder being programmable;

for altering the address positions of the common bus, common bus devices, other local buses and other local bus devices;

for allowing read only access to devices accessible via the common bus; and

for preventing access to selected devices of the system;

said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means in a desired arbitrating order, means for defining a common bus access cycle, means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or devices resident on the common bus, said signals representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding ones of the linked plurality of interface means in arbitration of the access requests; and

said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means.

6. A data processing apparatus comprising:

a plurality of computer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;

said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;

said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and

said shared memory means including a memory having a plurality of segments corresponding to the addresses of the plurality of connector means;

said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means in a desired arbitrating order, means for defining a common bus access cycle means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or devices resident on the common bus, said signals representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding ones of the linked plurality of interface means in arbitration of the access requests and further includes a plurality of common lock devices connected to the plurality of local buses of the plurality of local buses, said lock devices for providing status information of devices connected to the system and being addressable on each local bus for permitting devices resident on that local bus to request access to devices on the common bus or other local buses without having to access the common bus or other local buses to determine if these devices are available; and

said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means.

7. A data processing apparatus comprising:

a plurality of computer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;

said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;

said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and

said shared memory means including a memory having a plurality of segments corresponding to the addresses o the plurality of connector means;

said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means in a desired arbitrating order, means for defining a common bus access cycle, means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or devices resident on the common bus, said signals representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding one of the linked plurality of interface means in arbitration of the access requests; and

said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means and wherein the intercomputer interrupt means is connected to the common bus or local bus and includes a register designated for each of the plurality of computer means, said intercomputer interrupt device for addressing by any device and providing an interrupt signal at the time information is written into the register and is cleared when the interrupted device reads its register.

8. A data processing apparatus comprising;

a plurality of computer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;

said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;

said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and

said shared memory means including a memory having a plurality of segments corresponding to the addresses of the plurality of connector means;

said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means in a desired arbitrating order, means for defining a common bus access cycle, means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or decides resident on the common bus, said signals representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding ones of the linked plurality of interface means in arbitration of the access requests;

said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means; and

further including a plurality of resource monitors for the plurality of computer means, a system monitor connected to the plurality of resource monitors, and a mass storage device connected to the system monitor, each of said plurality of resource monitors including means for monitoring and controlling the operation of a corresponding computer means, and the system monitor including means for evaluating the system operation and detecting an error on the buses, and means for stopping operation of a failed computer means and replacing a failed computer means by another computer means by loading the information of the failed computer means into the other computer means.

9. A data processing apparatus comprising:

a plurality of computer means, a plurality of memories, a plurality of local buses, a plurality of bus interface means, a common bus, a shared memory means, and an intercomputer interrupt means;

said plurality of computer means being connected to the plurality of memories, the plurality of interface means and the common bus by the plurality of local buses, and the shared memory and intercomputer interrupt means connected to the common bus for information transfers over the common bus between the plurality of computer means, plurality of bus interface means, shared memory and intercomputer interrupt means;

said plurality of computer means coacting with the plurality of memory means for forming a plurality of individual data processor units including a plurality of peripheral device means, and a peripheral bus interconnecting the pluralities of computer means and peripheral device means for adding peripheral equipment to the system and providing an alternative interconnection between the computer cards selectable by an override signal of the common bus interface means protocol means for resolving contentions between the local bus devices and the peripheral bus devices, each computer means having an address and a protocol means for sending the addresses of processor units as access requests on a corresponding local bus to a corresponding one of the plurality of interface means; and

said shared memory means including a memory having a plurality of segments corresponding to the addresses of the plurality of connector means;

said plurality of interface means including a common bus arbitration protocol including means selectively linking together the plurality of interface means in a desired arbitrating order, means for defining a common bus access cycle, means for sequentially cycling the common bus access cycle and monitoring the local buses for computer means addresses occurring during each cycle, means coacting with the shared memory means for detecting signals addressing address spaces of selected computer means on local buses or decides resident on the common bus, said signals representing common bus access requests for information transfers, means for determining those information transfer requests requiring more than one cycle for completion, and interlocking means for interlocking memory segments requiring more than one cycle for transfer for response only to an access by the requesting computer means during subsequent cycles for completing the transfer of information, thereby providing for the unobstructed flow of data transfer information sequentially over the common bus to corresponding ones of the linked plurality of interface means in arbitration of the access requests; and

said intercomputer interrupt means including protocol means for providing interrupts to computer means connected to the local buses for interrupting access requests generated subsequently to an access request by a computer means when an information transfer is ready in response to a prior access request of the computing means.