Process for fabricating arbitrarily shaped through holes in a component

• US 4,871,418 A
• Filed: 03/23/1988
• Issued: 10/03/1989
• Est. Priority Date: 03/27/1987
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bayer, Thomas, Greschner, Johann, Bartha, Johann W., Wittlinger, Jurgen
• Primary Examiner(s): Schor, Kenneth M.
• Assistant Examiner(s): Anderson, Andrew J.
• Application Number:
  US07/172,736
• Time in Patent Office: 559 Days
• Field of Search: 156/628, 156/643, 156/644, 156/646, 156/659.1, 156/661.1, 156/668, 156/902
• US Class Current: 438/106
• CPC Class Codes: B26F 1/28 by electrical discharges
• CPC Class Codes: G03F 1/20 Masks or mask blanks for imaging by charged particle beam [CPB] radiation, e.g. by electron beam; Preparation thereof
• CPC Class Codes: G03F 7/00 Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor using photoresist structures for special production processes, see the relevant places, e.g. B44C, H01L, e.g. H01L21/00, H05K
• CPC Class Codes: G03F 7/12 Production of screen printing forms or similar printing forms, e.g. stencils
• CPC Class Codes: G03F 7/40 Treatment after imagewise removal, e.g. baking
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/4807 Ceramic parts
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0326 containing O
• CPC Class Codes: H05K 1/0393 Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 2201/0166 Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
• CPC Class Codes: H05K 3/0041 by plasma etching
• CPC Class Codes: H05K 3/42 Plated through-holes or plated via connections
• CPC Class Codes: Y10S 438/928 Front and rear surface processing

Abstract

According to a preferred embodiment, arbitrarily shaped holes are fabricated in 0.1 to 2 mm thick plates of polyoxymethylene homo- or copolymers. For that purpose, the polymeric substrate is photoresist-coated on either side; the desired pattern is simultaneously applied to both the front and the back side of the photoresist layers by imagewise exposure at optimum mask alignment; the photoresist layers are developed and blanket-exposed; the resultant photoresist structures are treated with a cyclic organosilicon compound and postbaked; the through holes are produced by sequential reactive ion etching of the polyoxymethylene from the front and the back side, each time down to a depth of about 2/3 of the substrate thickness; and the silylated photoresist masks are stripped from the front and the back side of the substrate.

Claims

1. Process for fabricating arbitrarily shaped through holes in a component, comprising the steps of:

A. producing photoresist mask on the front and back side of a substrate by;

(a) applying photoresist layers (2) to the front and back side of a substrate (1) of polymeric material, wherein the polymeric material comprises polyoxymethylene (POM) homo- or copolymers;

(b) simultaneously generating the desired pattern by imagewise exposure on the front and the back side of the photoresist layers (2);

(c) developing the photoresist layers (2);

B. fabricating the through holes by reactive ion etching (RIE) of the polymeric substrate (1), first from the front and then from the back side, each time until a predetermined etch depth has been obtained;

C. stripping the photoresist masks from the front and the back side of polymeric substrate (1)

2. Process according to claim 1 wherein the step of generating the desired pattern is accomplished by providing masks which are aligned to each other with an accuracy of about ±

1 to 2 μ

m.

3. Process according to claim 1 wherein the thickness of each photoresist layer is about 2 to 10 μ

m.

4. Process according to claim 1, characterized in that the substrate has a thickness of about 0.1 to 2 mm.

5. Process according to claim 4 characterized in that the substrate has a thickness of about 0.5 to 1 mm.

6. Process according to claim 4, further comprising treating the photoresist layers, after development and exposure, with a cyclic organosilicon compound and postbaking to increase their resistance in oxygen plasma during RIE.

7. Process according to claim 6, further comprising treating the photoresist layers with a solution of hexamethylcyclotrisilazane in xylene for about 90 min. at 40°

C. and then postbaking for about 5 min. at 90°

C.

8. Process according to claim 6, further comprising, after RIE, stripping the resulting silicon-containing photoresist masks in a stripper bath of about 44 percent KOH, while remaining in the bath for about 60 minutes at a bath temperature of about 70°

C.

9. Process according to claim 1 characterized in further comprising treating the surfaces of the substrate materials (1) with about 40 percent by volume sulphuric acid to improve the adhesion of the photoresist.

10. Process according to claim 1, characterized in that a phenolformaldehyde resin with a 3,4-dihydroxybenzophenone-4-[naphthoquinone(1,2)diazide(2)]-sulfonate as reactive constituent is applied as a photoresist.

11. Process according to claim 10 wherein the photoresist is postbaked for about 15 minutes at 80°

C.

12. Process according to claim 10, further comprising developing the exposed photoresist layers in a 1:

4 DI water diluted sodium borate and sodium hydroxide based developer and subsequently blanket irradiating with UV-light in a wavelength range of 200 to 450 nm.

13. Process according to claim 4, characterized in that a naphthoquinone-diazopolysiloxane is used as a photoresist.

14. Process according to claim 13, further comprising developing the exposed photoresist layers with 10 percent aqueous KOH or a 10 percent solution of tetramethylammoniumhydroxide in alcohol.

15. Process according to claim 13, further comprising postbaking the exposed photoresist layers for about 2 minutes at 80°

C., subsequently removing the non-exposed regions of the photoresist layers with an organic solvent.

16. Process according to claim 13, further comprising after RIE, stripping the silicon-containing photoresist masks in a stripper bath of about 44 percent KOH, while remaining in the bath for about 60 minutes at a bath temperature of about 70°

C.

17. Process according to claim 1, characterized in that imagewise exposure of the photoresist layers (2) with UV radiation is effected in a wavelength range of 200 to 450 nm.

18. Process according to claim 1, wherein the predetermined etch depth is about 2/3 of the substrate thickness.

19. Process according to claim 1, wherein multilayer ceramic chip carrier, circuit board or guide plate for fine metal wires used to build electrical test heads is produced.