Integrated Schottky diode and transistor

• US 4,871,686 A
• Filed: 03/28/1988
• Issued: 10/03/1989
• Est. Priority Date: 03/28/1988
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Davies, Robert B.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Gutierrez, Anthony
• Application Number:
  US07/173,795
• Time in Patent Office: 554 Days
• Field of Search: 437/39, 437/778, 437/201, 437/31, 437/175, 357/15
• US Class Current: 438/328
• CPC Class Codes: H01L 21/8222 Bipolar technology
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0766 with Schottky diodes only
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66212 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H03K 17/06 Modifications for ensuring a fully conducting state
• CPC Class Codes: H03K 17/063 in field-effect transistor switches

Abstract

An improved means and method is described for forming a Schottky diode integrated with transistors and other devices which is particularly useful where both control circuits and a large power device are on the same chip.

Nested N-, P-, N- and P+ regions are formed on an N+ semiconductor substrate. A portion of the overlying dielectric is removed adjacent one of the P+ regions over the N- region and a Schottky contact formed to the N- region and an ohmic contact to the adjacent P+ region. N+ and P+ regions are desirably provided where the junctions between the N-/P- regions and the P-/N- regions intersect the surface to provide contact to the N- and P- regions respectively.

A P region extends through the upper N- region and has U-shaped arms which partially overlie an annular shaped P+ region and is located between the active region of the PNP transistor and the collector contact to serve as a Kelvin probe. The arrangement is particularly valuable where a vertical PNP device without a buried collector region is required.

Claims

1. A process for forming a semiconductor device having an integral Schottky diode, comprising:

providing a semiconductor substrate of a first type and first impurity concentration and having a principal surface;

providing a first doped region of a second type opposite the first type and of a second impurity concentration and which forms a first junction with the substrate extending to the surface;

providing a second doped region of the first type and a third impurity concentration in the first region and which forms a second junction with the first region extending to the surface;

then in either order, (a) providing a third doped region of the second type and a fourth impurity concentration located at the intersection of the first junction and the surface and a fourth doped region of the second type and a fifth impurity concentration laterally within the second region at the surface, and (b) providing a fifth doped region of the first type and a sixth impurity concentration located at the intersection of the second junction and the surface;

exposing first, second and third portions of the surface, respectively, on the third, fourth and fifth doped regions and a fourth portion of the surface laterally within the second region adjacent to the second portion of the surface; and

providing a Schottky contact to the fourth portion of the surface and ohmic contact to the second portion of the surface.

2. The process of claim 1 further comprising covering the Schottky contact with a diffusion barrier conductor and then covering the diffusion barrier conductor with a further conductor.

3. The process of claim 1 wherein the impurity concentration at the surface of the second portion exceeds 10¹⁹ atoms/cm³ and the impurity concentration at the surface of the fourth portion is less than 10¹⁸ atoms/cm³.

4. The process of claim 3 wherein the impurity concentration at the surface of the second portion exceeds about 10²⁰ atoms/cm³ and the impurity concentration at the surface of the fourth portion is less than about 10¹⁷ atoms/cm³.

5. The process of claim 1 wherein the substrate is silicon and the Schottky contact comprises platinum and silicon.

6. The process of claim 1 wherein the fourth and fifth impurity concentrations are substantially the same.

7. The process of claim 1 wherein the third and fourth regions are formed substantially simultaneously.

8. The process of claim 1 wherein the steps of providing the fourth region and exposing the fourth portion comprise providing the fourth region substantially surrounding the fourth portion.

9. A process for forming a transistor having an integral Schottky diode, comprising:

providing a semiconductor substrate having a major surface, wherein the substrate has a first region of a first type and impurity concentration extending to the surface;

providing in the first region a second region of a second type opposite the first type and having a second impurity concentration and forming a first junction extending to the surface;

then in either order, (i) providing a third region of the first type, having a third impurity concentration, located laterally within the second region and forming a second junction extending to the surface, and (ii) providing a fourth region of the second type, having a fourth impurity concentration, having a first part located laterally within the third region at the surface, wherein the first part of the fourth region extends from the surface through the third region into the second region; and

forming a Schottky contact to a first portion of the surface of the third region adjacent the first part of the fourth region wherein the contact is shorted to the first part of the fourth region.

10. The process of claim 9 wherein the step of forming the fourth region comprises forming a second part located at the intersection of the first junction and the surface.

11. The process of claim 9 further comprising:

providing a fifth region of the second type and a fifth impurity concentration located laterally within the third region at the surface.

12. The process of claim 11 wherein the steps of providing the fourth and fifth regions, when viewed looking toward the surface, comprise providing the first part of the fourth region having U shaped arms and providing the fifth region at least partly between the U shaped arms.

13. The process of claim 11 wherein the steps of providing the fourth and fifth regions and the Schottky contact comprise providing the fifth region having an annular shape in the plane of the surface surrounding the first portion of the surface and providing the fourth region having U shaped arms overlapping the fifth region.

14. The process of claim 11 wherein the step of forming the Schottky contact comprises, exposing a second portion of the surface on the fifth region and the first portion of the surface on the third region adjacent the fifth region and thereafter simultaneously making a Schottky contact to the first portion of the surface and an ohmic contact to the second portion of the surface.

15. The process of claim 11 further comprising, providing in either order (i) a sixth region of the second type and a sixth impurity concentration at least partly in the second region at the surface and (ii) a seventh region of the first type and a seventh impurity concentration located at least partly in the third region at the surface, wherein the sixth and seventh regions are spaced apart.

16. The process of claim 9 where the step of providing a substrate with a first region comprises implanting a first dopant of the second type to a first depth and first dose and then implanting a second dopant of the second type to a second depth and second dose wherein the second depth is less than the first depth and the second dose is greater than the first dose.