Programmable logic device with array blocks connected via programmable interconnect

• US 4,871,930 A
• Filed: 05/05/1988
• Issued: 10/03/1989
• Est. Priority Date: 05/05/1988
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wong, Sau-Ching, Hartmann, Robert F., Kopec, Stanley J. Jr., So, Hock-Chuen
• Primary Examiner(s): Hudspeth, David
• Application Number:
  US07/190,663
• Time in Patent Office: 516 Days
• Field of Search: 307/465, 307/303, 307/468-469, 364/716
• US Class Current: 326/39
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.

Claims

1. A programmable logic device for producing a plurality of first signals, each of which is a programmable logical function of a plurality of second signals, each of which is applied to a respective one of a plurality of word line conductors, said programmable logic device comprising:

a plurality of first P-term line conductors, each of which is programmably interconnectable to each of said word line conductors for producing on each of said first P-term line conductors a third signal which is a logical function of the second signals applied to the word line conductors to which that first P-term line conductor is interconnected;

means for logically combining said third signals to produce a first of said first signals;

at least one second P-term line conductor which is programmably interconnectable to each of said word line conductors for producing on said second P-term line conductor a second of said first signals which is a logical function of the second signals applied to the word line conductors to which said second P-term line conductor is interconnected; and

means for applying said second of said first signals to one of said word line conductors as the second signal applied to that word line conductor, wherein said first and second P-term line conductors comprise a macrocell, and wherein said apparatus includes a plurality of said macrocells, said word line conductors being common to all of said macrocells.

2. The apparatus defined in claim 1 wherein the number of macrocells in said apparatus is greater than the number of said first P-term line conductors in any one of said macrocells.

3. The apparatus defined in claim 1 wherein the total number of said second P-term line conductors in said apparatus is greater than the number of first P-term line conductors in any one of said macrocells.

4. The apparatus defined in claim 1 wherein in any one macrocell, the number of said first P-term line conductors is greater than the number of said second P-term line conductors.

5. The apparatus defined in claim 1 wherein each of said first and second P-term line conductors is programmably interconnectable to each of said word line conductors via a programmable element selected from the group consisting of an EPROM transistor and an EEPROM transistor.

6. A programmable logic device comprising:

first and second logic array blocks respectively including (1) separate first and second pluralities of word line conductors;

(2) separate first and second pluralities of P-term line conductors, each of said P-term line conductors in said first plurality of P-term line conductors being programmably interconnectable only to each of said word line conductors in said first plurality of word line conductors, and each of said P-term line conductors in said second plurality of P-term line conductors being programmably interconnectable only to each of said word line conductors in said second plurality of word line conductors, for producing on each P-term line conductor a signal which is a logical function of the signals on the word line conductors to which that P-term line conductor is interconnected; and

(3) separate first and second means for respectively deriving a first output signal from at least one of said P-term line conductor signals associated with said first plurality of P-term line conductors and a second output signal from at least one of said P-term line conductor signals associated with said second plurality of P-term line conductors; and

programmable means for selectively applying said first output signal to at least one of the word line conductors in said second plurality of word line conductors.

7. The apparatus defined in claim 6 further comprising:

means for applying the output signal of said at least one logic array block to at least one of the word line conductors of said at least one logic array block.

8. The apparatus defined in claim 6 wherein at least one of said P-term line conductors signals in at least one of said logic array blocks is applied to at least one of the word line conductors of that logic array block and only that logic array block.

9. The apparatus defined in claim 6 wherein at least one of said P-term line conductor signals in at least one of said logic array blocks is applied only to one of the word line conductors of that logic array block.

10. The apparatus defined in claim 6 further comprising:

means for receiving an input signal applied to the programmable logic device; and

programmable means for selectively applying said input signal to at least one of the word line conductors of at least one of said logic array blocks.

11. The apparatus defined in claim 6 further comprising:

means for receiving an input signal applied to the programmable logic device; and

programmable means for, selectively applying said input signal to at least one of the word line conductors of either or both of said logic array blocks.

12. The apparatus defined in claim 6 wherein each of said P-term line conductors in each of said first and second logic array blocks is programmably interconnectable to each of said wordline conductors in the associated logic array block via a programmable element selected from the group consisting of an EPROM transistor and an EEPROM transistor.

13. The apparatus defined in claim 6 wherein said programmable means comprises a programmable element selected from the group consisting of an EPROM transistor and an EEPROM transistor.

14. The apparatus defined in claim 10 wherein said programmable means for selectively applying said input signal to at least one of the word line conductors of at least one of said logic array blocks comprises a programmable element selected from the group consisting of an EPROM transistor and an EEPROM transistor.

15. The apparatus defined in claim 11 wherein said programmable means for selectively applying said input signal to at least one of the word line conductors of either or both of said logic array blocks comprises a programmable element selected from the group consisting of an EPROM transistor and an EEPROM transistor.