Carrier recovery circuit for offset QPSK demodulators
First Claim
1. A carrier recovery circuit for recovering a frequency reference for first and second channels of a received offset QPSK (quadrature phase shift keying) modulated signal, each of said channels having a carrier recovery field and a bit timing recovery field (BTR), the carrier recovery field of each of said channels and the BTR of said first channel having a series of binary digits of identical logic values and the BTR of said second channel having a series of binary digits of alternating logic values, comprising:
- means including a voltage-controlled oscillator and a π
/2 phase shifter coupled to the oscillator for generating carriers of quadrature phase relationship;
first and second phase comparators for respectively detecting phase differences between said first and second channels of said offset QPSK modulated signal and said carriers;
delay means for introducing a delay of 1/2 symbol duration to a signal from one of said first and second phase comparators;
quadri-phase detector means having stable phase angles at π
/4, (3/4)π
, (5/4)π and
(7/4)π
radian for receiving a signal from said delay means and a signal from said second phase comparator;
BTR detector means connected to said second phase comparator for detecting the BTR of said second channel and generating a pulse upon the detection of said BTR;
selecting means for selecting a signal from said quadri-phase detector means in the absence of said pulse and briefly selecting a signal from said second phase comparator in the presence of said pulse; and
a loop filter for filtering the signal selected by said selecting means and supplying the filtered signal to said voltage-controlled oscillator as a frequency control signal.
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Accused Products
Abstract
A carrier recovery circuit comprises a voltage-controlled oscillator with a π/2 phase shifter coupled to it for generating carriers of quadrature phase relationship. First and second phase comparators respectively detect phase differences between an offset QPSK modulated signal and the carriers of the quadrature phase relationship. Signal from the first phase comparator is delayed by a 1/2 symbol duration and applied to one input of a quadri-phase detector having stable phase angles at π/4, (3/4)π, (5/4)π and (7/4)π radian and signal from the second phase comparator is applied to the other input of the quadri-phase detector. A bit timing recovery field (1010 . . . 1010) of the second channel is detected from the output of the second phase comparator. Signal from the quadri-phase detector is applied to a loop filter and thence to the voltage-controlled oscillator during the time when a bit timing recovery field (BTR) of the second channel is not still detected. To stabilize the operation of the carrier recovery loop of the circuit, the output of the second phase comparator from which that BTR is detected is briefly applied to the loop filter in response to the detection of a BTR of the second channel, instead of the signal from the quadri-phase detector.
166 Citations
5 Claims
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1. A carrier recovery circuit for recovering a frequency reference for first and second channels of a received offset QPSK (quadrature phase shift keying) modulated signal, each of said channels having a carrier recovery field and a bit timing recovery field (BTR), the carrier recovery field of each of said channels and the BTR of said first channel having a series of binary digits of identical logic values and the BTR of said second channel having a series of binary digits of alternating logic values, comprising:
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means including a voltage-controlled oscillator and a π
/2 phase shifter coupled to the oscillator for generating carriers of quadrature phase relationship;first and second phase comparators for respectively detecting phase differences between said first and second channels of said offset QPSK modulated signal and said carriers; delay means for introducing a delay of 1/2 symbol duration to a signal from one of said first and second phase comparators; quadri-phase detector means having stable phase angles at π
/4, (3/4)π
, (5/4)π and
(7/4)π
radian for receiving a signal from said delay means and a signal from said second phase comparator;BTR detector means connected to said second phase comparator for detecting the BTR of said second channel and generating a pulse upon the detection of said BTR; selecting means for selecting a signal from said quadri-phase detector means in the absence of said pulse and briefly selecting a signal from said second phase comparator in the presence of said pulse; and a loop filter for filtering the signal selected by said selecting means and supplying the filtered signal to said voltage-controlled oscillator as a frequency control signal. - View Dependent Claims (2, 3, 4, 5)
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Specification