Video interface for capturing an incoming video signal and reformatting the video signal

• US 4,872,054 A
• Filed: 06/30/1988
• Issued: 10/03/1989
• Est. Priority Date: 06/30/1988
• Status: Expired due to Fees

• Current Assignee: Trilon Dominion
• Original Assignee: Adaptive Video, Inc.
• Inventors: Franco, Michael J., Gray, Michael J.
• Primary Examiner(s): Peng, John K.
• Application Number:
  US07/213,028
• Time in Patent Office: 460 Days
• Field of Search: 358/140, 358/141, 358/148, 364/521, 364/413.13, 340/744, 340/747
• US Class Current: 348/441
• CPC Class Codes: G09G 1/285 Interfacing with colour displays, e.g. TV receiver
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level

Abstract

Video interface for converting a video input signal of one format to a video signal of a second format. Microprocessor control system stores executable script commands, identifying parameters of an incoming video signal and a desired outgoing video signal. An input video template is created, replicating all the pulse events contained in an input video signal. The template is phase locked with the incoming video signal synchronizing an internal pixel clock with the active line period of the incoming video signal. A video output template is created from the executable script for defining an output video signal timing format. The microprocessor-based system provides for complete diversity in capturing an input video signal of one format and converting the same to a different format for display or copying by a peripheral device.

Claims

1. A video interface for receiving a video input signal of one format and deriving an output video signal of another format comprising:

a microprocessor control system for generating a parameter list identifying the signal parameters of said input video signal including a pixel rate and a video signal line length, and for generating a parameter list identifying the signal parameters of said output signal, including the duration of horizontal and vertical synchronization pulses;

a pixel clock which is presettable to generate a pixel clock signal in accordance with said input parameter list, said pixel clock including a phase control input for receiving an error signal;

a synchronization signal processor for receiving synchronization signals related to said input video signal which identify an active line period and for receiving said pixel clock signal, said signal processor regenerating a local active line period signal identified by one ofsaid parameters from said pixel signal, and including means for comparing said regenerated active line period signal with said horizontal synchronization signals to derive said error signal for said pixel clock;

an analog-to-digital converter for receiving said input video signal and said pixel clock signal and generating a digital pixel value of said video signal under control of said pixel clock;

a graphics engine;

a display memory for storing each of said pixels having pixel values as a frame of pixels under control of said graphics engine;

an output synchronization generator for generating output horizontal and vertical synchronization pulses from said output parameter list; and

,

a digital-to-analog converter connected to receive said frame of pixels at an output pixel rate determined by said output parameter list in synchronization with said output synchronization generator horizontal and vertical synchronization pulses and converting said pixels to an analog voltage.

14. The video interface of claim 1, 2, 5 or 10, further comprising o digital data input/output port for transferring said stores pixels to an external digital device.

2. A video interface for receiving a video input signal of one format and deriving an output video signal of another format comprising:

a pixel clock generating a signal having a frequency presettable to pixel rate which is related to the pixel rate of an incoming video signal and having a control input for adjusting the phase of said pixel clock;

a sync processor for receiving a horizontal synchronization signal related to said incoming video signal and said pixel clock signal, said sync processor generating from said pixel clock signal a regenerated active line period signal, said sync processor including a phase detector means for comparing a period defined by said related horizontal synchronization signal with said regenerated active line signal period and deriving an error signal for said pixel clock, whereby said pixel clock phase is changed to reduce a phase error between said compared periods;

an analog-to-digital converter for receiving said video signal and converting said video signal into a plurality of digital pixels in synchronization with said pixel clock signal;

a display memory for storing said pixels;

a graphics engine connected to said display memory and said analog-to-digital converter for transferring said pixels to and from said display memory, forming a frame of said pixels;

an output synchronization signal generator for generating synchronization signals related to said output video signal; and

a lookup table for generating said output video signal from each of said stored pixels which are sequentially read by said graphics engine from said memory in synchronism with said output synchronization signals.

3. The video interface of claim 2 further comprising a digital-to-analog converter connected to receive said output signal and convert said signal to an analog video signal.

4. The video interface of claim 2 wherein said means for generating said output video signal is a lookup table which converts said digital pixels to a video signal.

5. A video interface for capturing a video signal frame and reformatting said frame in a different signal format comprising:

a microprocessor control system for storing parameters identifying a plurality of formats for an input video signal, including a raster line length and the width of synchronization pulses which terminate said raster line and for storing output parameters defining an output video signal;

a pixel clock having a presettable frequency and controllable phase;

a synchronization signal processor connected to receive said input video signal parameters from said control system and a signal from said pixel clock, regenerating from said pixel clock signal a video template identifying a plurality of synchronization signals having a duration identified by said input video signal parameters, said sync processor further including a comparator for comparing one of said regenerated signals with a synchronization signal component associated with said video frame signal and producing an error signal based on said comparison for modifying the phase of said pixel clock to reduce said error, whereby said video template is brought into synchronism with said input video signal parameters;

an analog-to-digital converter connected to digitize said video frame signal, producing a number of pixels which occur in time synchronism with said pixel clock;

a memory for storing said pixels;

a video signal processor connected to receive said regenerated signals and for storing said pixels at consecutive memory locations within said memory; and

,

said video signal processor reading said pixels from said memory at a rate determined by said output parameters relating to an output format received from said microprocessor control system.

6. The interface device of claim 5 further comprising a lookup table for converting said pixels read from said memory to a gray scale level identified by said parameters.

7. The interface device of claim 5 further comprising a digital-to-analog converter for converting each pixel of said memory to an analog voltage level.

8. The interface device of claim 5 wherein some of said parameters identify an output format and said sync processor regenerates output synchronization signals based on said parameters.

9. The interface device of claim 5 wherein one of said parameters identifies a reference level for said analog-to-digital converter.

10. A video interface for receiving a video input signal of one format and deriving an output video signal of a second format comprising:

a microprocessor operating system for executing instructions which initiate an acquisition of said input video signal, and a display of laid video signal, instructions including a first list of parameters for identifying said input video signal, and a second list of parameters for identifying said output video signal;

a programmable pixel clock generating a signal frequency selectable to an input video signal pixel rate identified by one of said input signal parameters, and a phase control input;

a sync processor for replicating each of the pulse events of said input video signals, said sync processor including means for generating time interval synchronized with said pixel clock signal, from one of said input signal parameters which defines the active line period of said input video signal, means for comparing said active video signal line period with said time interval, and means for generating a phase error signal based upon said comparison for correcting the phase of said pixel clock, and means for generating a remaining group of time intervals identifying each pulse event in said input video signal from said first list of parameters, and for generating a plurality of output video signal synchronization signals from said second list of parameters;

digitizing means connected to receive said input video signal active line portion and a digitizing signal synchronized with said pixel clock signal, and generating in response thereto a plurality of digital pixels;

a memory for storing each of said plurality of digital pixels as a frame of image data;

a graphics engine for reading said video image frame of data from said memory at a pixel rate identified by said output parameters in synchronization with said output synchronization signals; and

,

means for converting each of said digital pixels of said frame to a gray scale level constituting said output video signal.

11. The apparatus of claim 10 wherein said graphics engine is programmed to enhance said video image.

12. The apparatus of claim 10 wherein said means for converting is a lookup table programmed from said output parameter list.

13. The apparatus of claim 10, further comprising a programmable output synchronization signal generator for generating synchronization signal levels identified from said output parameter list. for generating said output video signal is a lookup table which converts said digital pixels to a video signal.

15. The video interface of claim 10 comprising a plurality of lists of parameters for identifying a plurality of different video input signal formats.

16. The video interface of claim 10 wherein said graphics engine is programmed to interpolate said video image.