Self restoring ferroelectric memory

• US 4,873,664 A
• Filed: 02/12/1987
• Issued: 10/10/1989
• Est. Priority Date: 02/12/1987
• Status: Expired due to Term

• Current Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Original Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Inventors: Eaton, S. Sheffield Jr.
• Primary Examiner(s): Moffitt, James W.
• Assistant Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US07/013,746
• Time in Patent Office: 971 Days
• Field of Search: 365/145, 365/149, 365/189, 365/222, 365/207
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A semiconductor memory uses cells with a ferroelectric capacitor having one plate coupled to a bit line by a FET and another plate coupled to a plate line. A pulse on the plate line causes the bit line to change voltage based on the state of the cell. A dummy cell arrangement is disclosed using one capacitor per cell, and another embodiment uses two capacitors per cell with no dummy. The cells cooperate with a sense amplifier and timing signals so that they are self restoring.

Claims

1. In a nonvolatile ferroelectric memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each said memory cell comprising a ferroelectric capacitor having first and second plate electrodes, the polarization of said capacitors corresponding to the data stored therewithin, the improvement wherein:

said memory further comprises a plurality of word lines and a plurality of plate lines distinct from said bit lines and word lines, each of the memory cells along a row being coupled to a word line corresponding to the row, each memory cell being coupled also to a corresponding plate line, each plate line being coupled to plate electrodes in a plurality of said cells,

each said memory cell further including a respective switching device located within the memory cell, said first plate electrode of said capacitor in said cell being coupled to its corresponding bit line via said switching device, said switching device being coupled to be controlled by said corresponding word line, said second plate electrode of said capacitor in said cell being coupled to said corresponding plate line.

2. The memory of claim 1 further comprising for each bit line, a respective sense amplifier coupled to said bit line and a dummy ferroelectric memory cell coupled to said sense amplifier, said dummy cell including therewithin a second switching device and a second ferroelectric capacitor, said capacitor having first and second plate electrodes, said first plate electrode being coupled via said second switching device to said sense amplifier, and a second plate line coupled to said second plate electrode of said second capacitor.

3. The memory of claim 2 wherein said first and second switching devices comprise field effect transistors each having gate electrodes coupled respectively to said word line and a second word line.

4. The memory of claim 1 wherein said switching device comprises a field effect transistor having a gate electrode coupled to be controlled by said word line.

5. The improvement of claim 1 further including a decoder, and wherein said plate line is further coupled to said decoder.

6. A nonvolatile ferroelectric memory comprising a plurality of ferroelectric memory cells arranged in rows and columns, each row corresponding to a word line, each column corresponding to first and second complementary, bit lines coupled to a respective sense amplifier,

each memory cell comprising first and second ferroelectric capacitors, each said capacitor having first and second plate electrodes, the first plate electrode of said first capacitor coupled selectively to said first bit line and the first plate electrode of said second capacitor coupled selectively to said second bit line;

each said memory cell including first and second access transistors each having a control electrode coupled to said corresponding word line, said first and second transistors being coupled respectively to the first plate electrodes of said first and second ferroelectric capacitors, each said transistor being located within said memory cell, said transistors being selectively actuable to couple said first plate electrodes of said capacitors to said first and second bit lines associated with said memory cell in response to a voltage on said word line;

said sense amplifier being responsive to a difference in voltage between said first and second bit lines;

said memory further including a plate line distinct from said bit lines, coupled to said second plate electrodes of both capacitors in a plurality of memory cells.

7. The memory of claim 6 wherein each said sense amplifier is responsive to a difference in voltages between said first and second bit lines to drive one of said bit lines to a first voltage and to maintain the other bit line at a reference voltage.

8. The memory according to claim 6 wherein said word line is parallel to said plate line.

9. The memory according to claim 6 wherein said word line is perpendicular to at least a portion of said plate line.

10. A nonvolatile ferroelectric memory comprising:

an array of memory cells organized into rows and columns;

a plurality of sense amplifiers, each column including a pair of bit lines coupled to a sense amplifier;

a plurality of word lines and plate lines, each said word line corresponding to a row of memory cells, each plate line being distinct from said word lines and said bit lines and being coupled to a plurality of memory cells;

each memory cell comprising two ferroelectric capacitors coupled to a corresponding plate line, a pair of transistors located within the memory cell and each coupled to said word line and to a respective said bit line, each said capacitor corresponding to a respective said transistor so that said capacitor can be coupled selectively to a corresponding said bit line; and

means for applying a voltage to a selected word line and a selected plate line to polarize one of said capacitors.

11. The memory according to claim 10 wherein said plate lines are parallel to said word lines.

12. The memory according to claim 11 wherein said plate lines are perpendicular to said word lines.

13. A nonvolatile ferroelectric memory comprising an array of memory cells arranged in rows and columns, each said memory cell comprising a pair of capacitors each employing ferroelectric material therein, said columns each including

a pair of complementary bit lines, a pair of transistors responsively coupled to a word line, said transistors being located within each memory cell and operable for coupling said capacitors of said memory cell to a pair of bit lines, and

sensing means coupled to said pair of bit lines, for driving said bit lines in accordance with the data content of said memory cell and for restoring the polarization of said memory cell capacitors.

14. The memory of claim 13 wherein said means coupling comprises switchable semiconductor devices coupled to a source of operating voltage.

15. The memory of claim 13 wherein said sensing means comprises a sense amplifier coupled to maintain a voltage on said bit lines after data from said memory cell has been read thereby to restore one of said capacitors.

16. A method of operating a nonvolatile semiconductor memory comprising the steps of:

storing complementary data in a memory cell having a pair of ferroelectric capacitors, said storing step including polarizing said capacitors in accordance with the data;

coupling said capacitors to a pair of bit lines via a pair of transistors;

applying a first signal across said capacitors until one said capacitor changes polarization, said applying step including controlling the voltage on a plate line distinct from said bit lines and coupled to both of said capacitors;

sensing said change of polarization, and driving said bit line pair in accordance with the data in said cell; and

thereafter

restoring said capacitors to their original polarization states by applying a voltage transition via said plate line to said capacitors while said bit lines are in a condition corresponding to the data sensed in the preceding step.

17. A non-volatile ferroelectric memory comprising an array of memory cells arranged in rows and columns, each said row corresponding to a respective word line, each said column corresponding to a respective bit line,

a respective sense amplifier coupled to each said bit line;

each memory cell comprising a ferroelectric capacitor having first and second plate electrodes and a transistor located within said cell for coupling said first electrode of said ferroelectric capacitor to the corresponding said bit line;

said word line being coupled to a control electrode of said transistor; and

a plate line coupled to the second plate electrode of said ferroelectric capacitor, said plate line being coupled to second plate electrodes of a plurality of capacitors in said array, said plate line being distinct from said word lines and said bit lines.

18. The memory of claim 17 further comprising a dummy cell coupled to said sense amplifier.

19. The memory of claim 17 further comprising a second ferroelectric capacitor coupled to said sense amplifier.

20. The memory of claim 17 wherein said transistor control electrode comprises the gate electrode of a field effect transistor.

21. The memory of claim 20 wherein said capacitor comprises a field effect transistor and the source-drain path of said transistor couples said one capacitor electrode to said bit line.

22. The memory of claim 17 further including a decoder and wherein said plate line is coupled to said decoder.

23. A nonvolatile method of reading data from and restoring data to a ferroelectric capacitor in a memory cell selected from an array of memory cells organized into rows and columns, each memory cell in the array including a respective ferroelectric capacitor and a switchable device located in the cell, where two polarization states of a said capacitor at a reference voltage correspond to two binary logic levels, comprising the steps of:

applying a signal to a word line along the row corresponding to the selected memory cell for turning on the switchable device located within the selected memory cell and thereby coupling one plate of said capacitor to a bit line corresponding to the column, and turning on other switchable devices for other cells along the word line in the same step;

applying a non-zero voltage across the plates of said capacitors in a plurality of said cells along the row while said switchable devices in said cells are turned on;

comparing the signal developed on a bit line corresponding to the selected memory cell to another signal thereby to determine the logic state of the data and terminating the nonzero voltage and the word line signal at different times.

24. The method of claim 23 further comprising applying a low voltage and a high voltage in a sequence to another plate of said ferroelectric capacitor while said switchable device is turned on, thereby restoring said capacitor to the polarization state prior to the read operation regardless of the logic state.

25. The method of claim 23 wherein said step of applying a non-zero voltage comprises applying a pulse to the other plate of said capacitor, said pulse terminating at a first trailing edge, said switchable device remaining turned on after said first trailing edge, and wherein said bit line is driven to a voltage level corresponding to the data read from said capacitor thereby to restore a ferroelectric polarization state to said capacitor.

26. The method of claim 25 wherein said steps of turning on a switchable device and applying a non-zero voltage commence simultaneously.

27. The method of claim 23 wherein said steps of turning on a switchable device and applying a non-zero voltage commence simultaneously.

28. The method of claim 23 wherein said comparing step comprises comparing said signal to another signal developed from a second ferroelectric capacitor.

29. The method of claim 28 wherein said comparing step includes operating a sense amplifier having one input coupled to said bit line, and having another input coupled to a second bit line which is coupled to said second ferroelectric capacitor.