Message FIFO buffer controller
First Claim
1. A control circuit for a FIFO (first in first out) memory circuit for providing address information to a FIFO memory means having an address field of n bits, said control circuit comprising:
- a first means for providing a first binary signal having n+1 bits;
a second means for providing a second binary signal having n+1 bits;
a first storage means for selectively receiving and storing the output of said first means;
second storage means for selectively receiving and storing the output of said second means;
first comparator means for comparing the output of said first storage means with the output of said second means and producing a first control signal indicative of said comparison; and
second comparator means for comparing the output of said second storage means with the output of said first means and producing a second control signal indicative of said comparison.
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Accused Products
Abstract
A FIFO (first in first out) control circuit for providing address information to a FIFO memory uses two up counters--one to provide the write address and one to provide the read address. A multiplexer selects which addresses (read or write) are used. Two storage registers are used to temporarily "hold" the output from the counters. This enables the counters to be re-loaded with their original "count" to enable either a re-reading or a re-writing of a message stored in the FIFO memory. Comparators and logic circuitry are used to provide two status output signals, namely full (or not) and empty (or not).
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Citations
8 Claims
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1. A control circuit for a FIFO (first in first out) memory circuit for providing address information to a FIFO memory means having an address field of n bits, said control circuit comprising:
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a first means for providing a first binary signal having n+1 bits; a second means for providing a second binary signal having n+1 bits; a first storage means for selectively receiving and storing the output of said first means; second storage means for selectively receiving and storing the output of said second means; first comparator means for comparing the output of said first storage means with the output of said second means and producing a first control signal indicative of said comparison; and second comparator means for comparing the output of said second storage means with the output of said first means and producing a second control signal indicative of said comparison. - View Dependent Claims (2, 3, 4)
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5. A control circuit for a FIFO (first in first out) memory circuit for producing address information to a FIFO memory means having an address field of n bits, said control device comprising:
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first counter means for providing a first binary signal having n+1 bits; second counter means for providing a second binary signal having n+1 bits; multiplexer means for receiving both said first signal and said second signal and selecting either said first or second signal as its output; first storage means for selectively receiving and storing the output of said first counter means; second storage means for selectively receiving and storing the output of said second counter means; first bus means for applying the output of sid first storage means to said first counter means; second bus means for applying the output of said second storage means to said second counter means; first comparator means for comparing the output of said first storage means with the output of said second counter means and producing a first control signal indicative of said comparison; and second comparator means for comparing the output of said second storage means with the output of said first counter means and producing a second control signal indicative of said comparison; whereby the n least significant bits output from said multiplexer are used to address said FIFO memory. - View Dependent Claims (6, 7, 8)
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Specification