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Message FIFO buffer controller

  • US 4,873,666 A
  • Filed: 10/15/1987
  • Issued: 10/10/1989
  • Est. Priority Date: 10/14/1987
  • Status: Expired due to Term
First Claim
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1. A control circuit for a FIFO (first in first out) memory circuit for providing address information to a FIFO memory means having an address field of n bits, said control circuit comprising:

  • a first means for providing a first binary signal having n+1 bits;

    a second means for providing a second binary signal having n+1 bits;

    a first storage means for selectively receiving and storing the output of said first means;

    second storage means for selectively receiving and storing the output of said second means;

    first comparator means for comparing the output of said first storage means with the output of said second means and producing a first control signal indicative of said comparison; and

    second comparator means for comparing the output of said second storage means with the output of said first means and producing a second control signal indicative of said comparison.

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