Sequential read access of serial memories with a user defined starting address

• US 4,873,671 A
• Filed: 01/28/1988
• Issued: 10/10/1989
• Est. Priority Date: 01/28/1988
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Lucero, Elroy M., Kowshik, Vikram, Boddu, Sudhakar
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Garcia, Alfonso
• Application Number:
  US07/149,399
• Time in Patent Office: 621 Days
• Field of Search: 365/230, 365/189, 365/239, 365/236, 365/240, 365/78, 365/221, 377/76, 377/69, 377/70
• US Class Current: 365/189.12
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413

Abstract

Circuitry for serial read memory access utilizing a random starting address is disclosed. Fast read access is provided without upsetting the original data pattern stored in the memory core if the sequential read is terminated in midstream. After the last memory address is reached, the access automatically rolls over to the first address. The circuit provides both random and sequential access functions and allows the memory to be used as a shift register of variable length.

Claims

1. Apparatus for reading a sequential series of storage registers within a memory array wherein the memory array includes a plurality of storage registers organized for read access by having sequential binary addresses associated therewith, each storage register having capacity for storing data comprising a plurality of data bits, the apparatus comprising:

(a) address register/counter means for storing a binary address which is used to access a preselected storage register within the memory array to serially read the data bits from the preselected storage register, the address register/counter means including means for incrementing the stored binary address by 1 upon receipt of an increment signal; and

(b) means for determining that all of the plurality of data bits stored in the preselected storage register have been read from the preselected storage register and for generating the increment signal in response to said determination such that data is read from storage registers within the memory array having sequential binary addresses, whereby the apparatus automatically initiates a read of a sequence of storage registers in the array, the read sequence comprising a variable number of storage registers.

2. A method for reading a plurality of sequential data storage registers within a memory array, the method comprising the steps of:

(a) accessing a preselected storage register within the array utilizing a binary address corresponding to the preselected storage register,

(b) reading data from the preselected storage register;

(c) sensing that data has been read from the preselected storage register;

(d) upon sensing that data has been read from the preselected storage register, automatically incrementing by 1 the binary address utilized to access the preselected storage register; and

(e) repeating steps (a)-(d) above utilizing the incremented binary addresses to read each of a plurality of sequential data storage registers within the memory array, thereby initiating the read of sequence of storage registers in the array, the read sequence comprising a variable number of storage registers.

3. A method as in claim 2 wherein the sequence of incremented binary addresses is returned to the first address in the sequence after the Nth data storage register has been read such that all N registers in the memory array are used.

4. Serial read access circuitry for reading sequential storage registers within a memory array of the type that includes a plurality of storage registers organized for read access by having sequential binary addresses associated therewith, each storage register having capacity for storing data comprising a plurality of data bits, the serial read access circuitry comprising:

(a) an instruction shift register that serially receives a read instruction comprising a plurality of data bits, the read instruction including the binary address of a preselected storage register within the memory array, the instruction shift register including means responsive to receipt by the instruction shift register means of all of the plurality of data bits of the read instruction for generating a latch signal;

(b) an address register/counter that stores the binary address of a storage register to be read, the address register/counter including means for incrementing by 1 the binary address stored therein in response to an increment signal, the address register/counter being responsive to the latch signal for receiving the binary address of the preselected storage register from the instruction shift register as the address stored therein;

(c) a data shift register that receives the plurality of data bits stored in the preselected storage register and provides the received data bits as an output in serial form; and

(d) a data stream counter that counts the number of data bits provided by the data shift register and generates the increment signal when all of the plurality of data bits have been transferred from the data shift register, whereby the binary address stored in the address register/counter is incremented by 1 such that the storage register in the memory array having the next sequential address is read, whereby the serial read access circuitry automatically initiates a read of a sequence of storage registers in the array, the read sequence comprising a variable number of storage registers.