Auto-threshold/adaptive equalizer

• US 4,873,700 A
• Filed: 10/14/1987
• Issued: 10/10/1989
• Est. Priority Date: 10/14/1987
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Wong, Hee
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US07/108,718
• Time in Patent Office: 727 Days
• Field of Search: 375/76, 375/20, 375/28, 307/355, 307/356, 307/357, 307/358, 307/359, 328/146, 328/164
• US Class Current: 375/317
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/063 Setting decision thresholds using feedback techniques only

Abstract

An auto-threshold circuit in accordance with the present invention comprises a full-wave peak sensor for accurately estimating slice levels for input signal detection. The peak sensor is qualified such that the auto-threshold circuit does not track an input signal with no modulation. The input signal is windowed with a phase-locked-loop so that the peak sensor is coherent to the input signal, causing the circuit to be insensitive to noise spikes or input distortion outside the window. The auto-threshold circuit includes a digital loop filter which receives the output from an auto-threshold controller and generates a corresponding binary signal which is converted by a digital Sigma/delta modulator to a single bit pulse density modulated signal having a predetermined sampling frequency. An adaptive equalizer in accordance with the present invention shares the auto-threshold slicing signal for generating its error feedback signal. The adaptive equalizer comprises a frequency selector which generates an output signal in response to the input signal and the feedback signal. As stated above, a threshold comparator slices the equalizer output at predetermined levels. A controller receives the comparator output and provides a controller output representative of the voltage level of the comparator output. A digital filter is then utilized to generate a corresponding binary signal as the feedback signal to the frequency selector. The adaptive equalizer is operable at more than one speed.

Claims

1. An auto-threshold circuit that allows a signal receiver to detect an input signal at different amplitude levels, the input signal comprising data and a carrier waveform, the auto-threshold circuit comprising

window comparator means for slicing the input signal at predetermined levels;

an auto-threshold controller which receives the sliced input signal and provides an output voltage representative of the sliced input signal;

a digital loop filter which receives the output voltage of the auto-threshold controller and generates a corresponding binary signal; and

converter means for converting the binary signal to a single-bit, pulse density modulated signal having a predetermined sampling frequency whereby the auto-threshold circuit provides selected data as an ouput.

2. An auto-threshold circuit as in claim 1 wherein the converter means comprises a digital Sigma/delta modulator.

3. An auto-threshold circuit as in claim 2 wherein the auto-threshold control voltage generated form the digital Sigma/delta modulator is filtered by an RC circuit with a non-critical time constant.

4. An auto-threshold circuit as in claim 1 and further including means for operating the digital loop filter at more than one speed.

5. An auto-threshold circuit as in claim 1 and further including an adaptive equalizer that receives the auto-threshold slicing signal and generates an error feedback signal as an input to the adaptive equalizer.

6. An auto-threshold circuit as in claim 1 and including means for qualifying the auto-threshold controller to provide selected data as an output.

7. An auto-threshold circuit as in claim 6 wherein the means for qualifying comprises means for providing a first qualifier signal to the autothreshold controller, the first qualifier signal comprising a sliced output from 0+ and 0- filters.

8. In a receiver of the type that recovers data from input signals comprising data and a carrier waveform, an auto-threshold circuit that allows the receiver to detect input signals at different amplitude levels, the auto-threshold circuit comprising

full-wave peak sensing means for estimating slice levels for input signal detection;

means for qualifying the peak sensing means such that the auto-threshold circuit provides selected data as an output; and

means for providing a window for the input signal such that the peak sensing means is coherent to the input signal, whereby the auto-threshold circuit is insensitive to noise spikes or input signal distribution outside the window.

9. An auto-threshold circuit that allows a signal receiver to detect an input signal at different amplitude levels, the auto-threshold circuit comprising

window comparator means for slicing the input signal at predetermined levels;

an auto-threshold controller which receives the sliced input signal and provides an output representative of the voltage level of the sliced input signal;

means for qualifying the auto-threshold controller such that the auto-threshold circuit does not track an input signal with no modulation, wherein the means for qualifying provides first and second qualifier signals to the auto-threshold controller, the first qualifier signal being a sliced output from 0+ and 0- filters, the second qualifier signal enabling the auto-threshold circuit to operate on the same input signal segments as an adaptive equalizer included in the receiver;

a digital loop filter which receives the output of the auto-threshold controller and

generates a corresponding binary output signal; and

converter means for converting the binary output signal to a single bit pulse density modulated signal having a predetermined sampling frequency.

10. An auto-threshold circuit as in claim 9 wherein the qualifying means further includes means for providing a third qualifier signal to the controller, the third qualifier signal preventing the auto-threshold circuit from responding to bits which may contain distortion due to bus contention.