Heart pacemaker
First Claim
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1. A cardiac pacemaker, comprising:
- means for applying stimulating pulses to the heart of the patient at a rate determined by a pacing parameter;
means for detecting a first physiological parameter which is correlated with physical exertion of the patient and producing a first output signal representative of said first physiological parameter;
a memory having a plurality of memory locations containing data;
a means for producing a first address signal as a function of said first physiological parameter;
a means for producing at least one further address signal;
a means for addressing said plurality of memory locations as a function of said first address signal and said further address signal and for outputting the addressed data as a second output signal;
circuitry means receiving said first output signal for varying the pacing parameter as a function of said first output signal, said circuitry means being controllable by the addressed data received by said circuitry means.
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Abstract
A cardiac pacer features plural addressable digital memory elements each containing different pulse parameters for the pacing stimulation, address-selecting digital logic circuitry for choosing the characteristics of the pulses to be generated in response to signals derived from plural physiological sensors detecting different exercise-related body functions to improve control of the heart during various levels of exertion.
47 Citations
10 Claims
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1. A cardiac pacemaker, comprising:
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means for applying stimulating pulses to the heart of the patient at a rate determined by a pacing parameter; means for detecting a first physiological parameter which is correlated with physical exertion of the patient and producing a first output signal representative of said first physiological parameter; a memory having a plurality of memory locations containing data; a means for producing a first address signal as a function of said first physiological parameter; a means for producing at least one further address signal; a means for addressing said plurality of memory locations as a function of said first address signal and said further address signal and for outputting the addressed data as a second output signal; circuitry means receiving said first output signal for varying the pacing parameter as a function of said first output signal, said circuitry means being controllable by the addressed data received by said circuitry means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification