Etching method for generating apertured openings or trenches in layers or substrates composed of n-doped silicon

• US 4,874,484 A
• Filed: 05/13/1988
• Issued: 10/17/1989
• Est. Priority Date: 05/27/1987
• Status: Expired due to Term

• Current Assignee: Epcos AG (TDK Corporation)
• Original Assignee: Siemens AG
• Inventors: Lehmann, Volker, Foell, Helmut
• Primary Examiner(s): Valentine, Donald R.
• Application Number:
  US07/193,760
• Time in Patent Office: 522 Days
• Field of Search: 204/129.3, 204/129.35, 204/129.65, 204/129.55, 204/129.75
• US Class Current: 438/750
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: H01L 29/102 Cathode base regions of thyristors
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/7392 with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
• CPC Class Codes: H01L 29/744 Gate-turn-off devices
• CPC Class Codes: H01L 29/92 Capacitors having potential barriers
• CPC Class Codes: H01L 29/93 Variable capacitance diodes, e.g. varactors

Abstract

The present invention provides the production of apertured openings or trenches in layers or substrates composed of n-doped silicon proceeding in an electrolytic way, whereby the silicon is connected as a positively polarized electrode of an electrolysis cell containing an agent that contains hydrofluoric acid. Hole structures having highly variable cross-section can be reproducibly manufactured with the method of the invention and holes can be localized by prescribing nuclei. The invention can be used in the manufacture of trench cells in memory modules, insulating trenches in LSI semiconductor circuits, large-area capacitors (varicaps), and in contacting more deeply disposed layers in disconnectable and voltage-controlled thyristors.

Claims

1. A method for generating apertured openings of trenches in substrates composed of n-silicon, as used in the manufacture of semiconductor components, especially LSI semiconductor circuits, through masked etching, wherein an electrolytic etching is carried out in an electrolyte containing hydrofluoric acid, through the application of a constant or chronologically varying potential, the silicon substrate being connected as a positively polarized electrode of an electrolysis cell, the electrolysis being injected by illuminating the silicon member proceeding from a backside and a structured silicon nitride layer is used as an etching mask.

2. A method for generating apertured openings of trenches in substrates composed of n-silicon, as used in the manufacture of semiconductor components, especially LSI semiconductor circuits, through masked etching, wherein an electrolytic etching is carried out in an electrolyte containing hydrofluoric acid, through the application of a constant or chronologically varying potential, the silicon substrate being connected as a positively polarized electrode of an electrolysis cell, the electrolysis being injected by illuminating the silicon member proceeding from a backside and a chemical etching is also performed before and/or after the electrolytic etching.

3. The method of claim 2 wherein the chemical etching is carried out in a caustic solution.

4. A method for generating apertured openings of trenches in substrates composed of n-silicon, as used in the manufacture of semiconductor components, especially LSI semiconductor circuits, through masked etching, wherein an electrolytic etching is carried out in an electrolyte containing hydrofluoric acid, through the application of a constant or chronologically varying potential, the silicon substrate being connected as a positively polarized electrode of an electrolysis cell, the electrolysis being injected by illuminating the silicon member proceeding from a backside and a wetting agent is added to the electrolyte.

5. The method of claim 4 wherein the wetting agent is based on formaldahyde.

6. A method for generating apertured openings of trenches in substrates composed of n-silicon, as used in the manufacture of semiconductor components, especially LSI semiconductor circuits, through masked etching, wherein an electrolytic etching is carried out in an electrolyte containing hydrofluoric acid, through the application of a constant or chronologically varying potential, the silicon substrate being connected as a positively polarized electrode of an electrolysis cell, the electrolysis being injected by illuminating the silicon member proceeding from a backside and a wet etching is carried out in a 1 to about 10 weight percent caustic potash solution with an etching time of 10 minutes.

7. A method for generating apertured openings of trenches in substrates composed of n-silicon, as used in the manufacture of semiconductor components, especially LSI semiconductor circuits, through masked etching, wherein an electrolytic etching is carried out in an electrolyte containing hydrofluoric acid, through the application of a constant or chronologically varying potential, the silicon substrate being connected as a positively polarized electrode of an electrolysis cell, the electrolysis being injected by illuminating the silicon member proceeding from a backside and a pre-etching is carried out in a 10 weight percent caustic potash solution with an etching time of 10 minutes.

8. A method for manufacturing semiconductor components including the steps of generating controlled hole geometries and trenches in a silicon substrate through masked etching by using an electrolytic etching in an electrolyte containing hydrofluoric acid, with a constant or chronologically varying potential, and using a chemical etching before the electrolytic etching.

9. The method of claim 8 including the step of injecting the electrolysis by illuminating the silicon substrate.