Method of testing semiconductor wafers

• US 4,875,002 A
• Filed: 11/24/1987
• Issued: 10/17/1989
• Est. Priority Date: 05/30/1984
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Sakamoto, Hideo, Tsugita, Hiroshi
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Nguyen, Vinh P.
• Application Number:
  US07/129,895
• Time in Patent Office: 693 Days
• Field of Search: 324/73 R, 324/73 AT, 324/158 R, 324/158 F, 324/73 PC, 371/25, 371/20, 371/15, 437/8, 364/552, 364/490
• US Class Current: 324/73.1
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Semiconductor wafers are tested more efficiently with an improved throughput. Since a plurality of test items are involved but some tests discover more defects than the others, and since neighboring wafers may be believed to have similar characteristics regarding defects, a spot-checking routine and a preferred sequence in which the plurality of tests are conducted may be selected from the data collected and stored from a preliminary testing so that defective samples are more efficiently identified.

Claims

1. A method of testing wafers with many chips thereon comprising the steps of

conducting tests of a plurality of kinds on chips on said wafers during a predetermined initial period,

counting the number of wafers which failed in each of said plurality of kinds of tests,

storing said numbers, and

automatically selecting one or more of said plurality of kinds of tests for subsequent testing of wafers on the basis of said stored numbers.

2. The method of claim 1 wherein said plurality of tests are conducted during said predetermined initial period in a predetermined sequence.

3. The method of claim 1 wherein said plurality of tests are conducted at specified positions of said wafers.

4. A method of testing chips on semiconductor wafers comprising the steps of

performing a spot-checking test on every nth one of said chips, n being a preselected integer greater than 1,

generating either a "good" or a "bad" signal according to whether the result of said test was satisfactory or not satisfactory, respectively,

resuming said spot-checking test step if a "good" signal is generated, and

stopping said spot-checking test step if a "bad" signal is generated and immediately thereupon testing m successive chips which follow, m being another preselected integer greater than 1.

5. The method of claim 4 wherein m is greater than n.

6. A method of testing wafers comprising the steps of obtaining data on defects discovered by a plurality of tests conducted in a sequence on chips at specified positions on a wafer, said data being classified according to said positions of said chips on said wafer, storing said data in a memory means, and causing said sequence of said plurality of tests on another chip to be changed according to said data in such a way that a test which discovers defects more frequently at the position of said another chip is conducted with high priority, whereby defective chips are injected efficiently.