Silicon-on-insulator integrated circuits and method

• US 4,875,086 A
• Filed: 05/22/1987
• Issued: 10/17/1989
• Est. Priority Date: 05/22/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chang, Peng-Heng, Shen, Chi-Cheong, Malhi, Satwinder D. S., Bean, Kenneth E.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US07/053,440
• Time in Patent Office: 879 Days
• Field of Search: 357/59, 357/54, 357/73, 357/59
• US Class Current: 257/506
• CPC Class Codes: H01L 23/4825 for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors
• CPC Class Codes: H01L 29/78639 with a drain or source connected to a bulk conducting substrate
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Preferred embodiments include silicon-on-insulator structures (30) and integrated circuits include a thin single crystal silicon layer (32) on a silicon dioxide layer (34) which is on a polysilicon layer (36) bonded to a surface-oxidized silicon substrate (42) by a glass layer (38). Also, single crystal silicon layers on oxide on polysilicon substrates and methods of fabrication are included in the preferred embodiments.

Claims

1. An integrated circuit, comprising:

(a) a silicon layer with active devices;

(b) said silicon layer on an insulating layer;

(c) said insulating layer on a buffer layer; and

(d) a glass layer bonding said buffer layer to a substrate, said glass layer of composition characterized by heating of a mixture of glass paticles in a liquid between said buffer layer and said substrate to partially drive off and partially decompose said liquid plus fire said glass particles.

2. The integrated circuit of claim 1, wherein:

(a) said insulating layer is silicon dioxide;

(b) said buffer layer is polysilicon;

(c) said substrate is silicon; and

(d) said glass layer includes PbO and SiO₂.

3. The integrated circuit of claim 2, wherein:

(a) said silicon layer is less than 1.0 μ

m thick.

4. The integrated circuit of claim 2, wherein:

(a) said silicon layer is less than 60 μ

m thick and includes a heavily doped buried layer adjacent said insulating layer.

5. The integrated circuit of claim 1, wherein:

(a) said buffer layer is rigid to stress isolate said silicon layer from said glass layer and substrate.

6. The integrated circuit of claim 1, wherein:

(a) said buffer layer is a barrier to reaction of said insulating layer with said glass.

7. The integrated circuit of claim 1, wherein:

(a) said glass layer is more than 10 μ

m thick.

8. The integrated circuit of claim 1, wherein:

(a) said glass layer is characterized by essentially no contaminant emissions at processing temperatures of 1,000°

C.

9. The integrated circuit of claim 1, wherein:

(a) said silicon contacts said buffer layer through at least one via in said insulating layer; and

(b) said buffer layer is n⁺ doped polysilicon.

10. A silicon-on-insulator structure, comprising:

(a) a silicon substrate with a silicon dioxide layer on a first surface;

(b) a glass bonding layer on said silicon dioxide layer;

(c) a buffer layer on said glass bonding layer, said glass bonding layer of composition characterized by heating of a mixture of glass paticles in a liquid between said buffer layer and said silicon dioxide layer to partially drive off and partially decompose said liquid plus fire said glass particles;

(d) an insulation layer on said buffer layer; and

(e) a layer of single crystal silicon on said insulation layer.

11. The structure of claim 10, wherein:

(a) said glass bonding layer includes PbO, SiO₂, and Al₂ O₃ ;

(b) said buffer layer is polysilicon; and

(c) said insulation layer is silicon dioxide.

12. An integrated circuit, comprising:

(a) a silicon layer with active devices;

(b) said silicon layer on an insulating layer;

(c) said insulating layer on a buffer layer; and

(d) a glass layer bonding said buffer layer to a substrate, said glass layer of thickness greater than about 10 microns.

13. The integrated circuit of claim 12, wherein:

(a) said insulating layer is silicon dioxide;

(b) said buffer layer is polysilicon;

(c) said substrate is silicon; and

(d) said glass layer includes PbO and SiO₂.