Peripheral emulation apparatus
First Claim
1. In a data processing system having a first processor generating address and data signals, at least one peripheral unit having a plurality of registers for storing parameter data which controls the operation of said peripheral unit, at least selected ones of said registers being device specific registers, and means responsive to said address and said data signals for transferring said parameter data from said first processor to said registers, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit, said apparatus comprisingmeans responsive to said address and said data signals for generating a flag signal when said parameter data is being transferred from said first processor to said device specific registers;
- means responsive to said flag signal for temporarily disconnecting said first processor from said peripheral unit; and
means responsive to said address and data signals for providing and writing alternate parameter data into said device specific registers.
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Accused Products
Abstract
Control apparatus allows application software written for use with peripheral devices manufactured by one company to run with other peripheral devices. The apparatus intercepts device-specific control commands generated by the software and translates the commands into commands which are compatible with the peripheral connected to the system. Non-device specific commands are passed untranslated through the control apparatus to the peripheral. More specifically, registers within the control apparatus which must be programmed with parameters unique to a particular peripheral cannot be accessed by the application software while other nonspecific registers remain read and write accessible. Peripheral-specific parameters are instead changed by a secondary processor which uses special hardware to minimize interference with the main processor.
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Citations
19 Claims
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1. In a data processing system having a first processor generating address and data signals, at least one peripheral unit having a plurality of registers for storing parameter data which controls the operation of said peripheral unit, at least selected ones of said registers being device specific registers, and means responsive to said address and said data signals for transferring said parameter data from said first processor to said registers, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit, said apparatus comprising
means responsive to said address and said data signals for generating a flag signal when said parameter data is being transferred from said first processor to said device specific registers; -
means responsive to said flag signal for temporarily disconnecting said first processor from said peripheral unit; and means responsive to said address and data signals for providing and writing alternate parameter data into said device specific registers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. In a data processing system having a first processor generating address, data and an enable signal, at least one peripheral unit having a plurality of registers for storing device-specific parameter data which controls the operation of said peripheral unit, a data bus connecting said processor and said registers for transferring said parameter data from said first processor to said registers, and means responsive to said enable signal for causing parameter data on said data bus to be written into said registers, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit, said apparatus comprising,
a second processor, means responsive to changes in selected ones of said data signals for alerting said second processor that said first processor has attempted or will attempt to write parameter data into said registers, said second processor thereupon generating a flag signal, first gate means connected in said data bus between said first processor and said peripheral unit and responsive to said flag signal for temporarily disconnecting said first processor from said peripheral unit, and means responsive to said address and data signals for generating an alternative enable signal and for writing alternate parameter data from said second processor into said registers.
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14. A data processing system comprising,
a first processor having means for generating address signals, data signals and control signals, at least one peripheral unit having a plurality of registers for storing device-specific parameter data which controls the operation of said peripheral unit, a data bus connecting said first processor and said registers for transferring said parameter data from said first processor to said registers, means responsive to one of said control signals generated by said first processor for enabling parameter data on said data bus to be written into said registers, a mode register for storing parameters which control the operation of said data processing system, a second processor having means for generating data and control signals, means responsive to changes in mode signals stored in said mode register for alerting said second processor that said first processor has attempted or will attempt to write parameter data into said registers, said second processor thereupon generating a flag signal, first gate means connected in said data bus between said first processor and said peripheral unit and responsive to said flag signal for temporarily disconnecting said first processor from said peripheral unit, and a multiplexer, responsive to said flag signal for disconnecting the control signals generated by said first processor from said peripheral unit and for connecting data and control signals generated by said second processor to said peripheral unit, said second processor thereupon writing alternate parameter data into said registers.
Specification