Semiconductor memory with an improved nibble mode arrangement
First Claim
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1. A semiconductor memory comprising:
- a plurality a memory arrays each of which includes a plurality of dynamic memory cells;
a plurality of read circuits coupled respectively to said memory arrays;
a timing generator which detects every change in a column address strobe signal applied to said semiconductor memory, wherein said timing generator includes means to form timing signals in response to said detected changes; and
a control circuit which, upon receipt of said timing signals, produces control signals to successively operate said plurality of read circuits so that said semiconductor memory successively produces output data in synchronism with every change in said column address strobe signal in read operation.
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Abstract
A dynamic semiconductor memory includes a shift register which enables a nibble operation to be carried out, and a timing generator. The timing generator detects every transient state of the column address strobe signals to form shift pulses that are to be supplied to said shift register, as well as timing signals that are to be supplied to various internal circuits. The dynamic semiconductor memory having such a timing generator operates at high speeds, since it is accessed by the cycle number with a small change of the column address strobe signals.
142 Citations
15 Claims
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1. A semiconductor memory comprising:
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a plurality a memory arrays each of which includes a plurality of dynamic memory cells; a plurality of read circuits coupled respectively to said memory arrays; a timing generator which detects every change in a column address strobe signal applied to said semiconductor memory, wherein said timing generator includes means to form timing signals in response to said detected changes; and a control circuit which, upon receipt of said timing signals, produces control signals to successively operate said plurality of read circuits so that said semiconductor memory successively produces output data in synchronism with every change in said column address strobe signal in read operation. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor memory comprising:
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a plurality of memory arrays each of which includes a plurality of dynamic memory cells; a plurality of read circuits coupled, respectively, to said memory arrays so that each memory array is coupled to a predetermined read circuit; and a timing generator for producing a plurality of control signals to successively operate said plurality of read circuits comprising; a shift register having a plurality of successive stages coupled, respectively, to said plurality of read circuits, a signal generator circuit coupled to said shift register for generating a plurality of shift signals to said shift register in response to detecting every change in a column address strobe signal applied to said semiconductor memory, wherein said shift signals operate said shift register to shift stages to successively operate said plurality of read circuits respectively coupled to said plurality of shift register stages in synchronism with every change in said column address strobe signal in read operation. - View Dependent Claims (7)
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8. A dynamic memory receiving first address signals in response to a predetermined change in a row address strobe signal and second address signals in response to a predetermined change in a column address strobe signal, said dynamic memory comprising:
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a plurality of memory arrays; a plurality of read circuits coupled, respectively, to said memory arrays so that each memory array is coupled to a predetermined read circuit; an output terminal coupled to receive output data read out from said plurality of memory arrays by said plurality of read circuits; a timing generator which detects every change in said column address strobe signal, wherein said timing generator includes means to form timing signals in response to said detected changes; and control means responsive to said timing signals for producing control signals to successively operate said plurality of read circuits so that said dynamic memory successively produces output data in synchronism with every change in said column address strobe signal in read operation. - View Dependent Claims (9, 10)
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11. A dynamic memory receiving first address signals in response to a predetermined change in a row address strobe signal and second address signals in response to a predetermined change in a column address strobe signal, said dynamic memory comprising:
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mode determining means responsive to said row and column address strobe signals for determining a mode in said dynamic memory; a plurality of memory arrays; a plurality of read circuits coupled, respectively, to said memory arrays so that each memory array is coupled to a predetermined read circuit; an output terminal coupled to receive output data read out from said plurality of memory arrays by said plurality of read circuits; a timing generator which detects every change in said column address strobe signal and which forms timing signals in response to the detected changes, when said mode determining means indicates a predetermined mode; and control means responsive to said timing signals for producing control signals to successively operate said plurality of read circuits so that said dynamic memory successively produces output data in synchronism with every change in said column address strobe signal in read operation. - View Dependent Claims (12, 13, 14, 15)
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Specification