Method for fabricating an isolation region in a semiconductor substrate

• US 4,876,214 A
• Filed: 06/02/1988
• Issued: 10/24/1989
• Est. Priority Date: 06/02/1988
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Yu, Simon, Lane, Eric, Patton, Evan, Yamaguchi, Tadanori
• Primary Examiner(s): Chaudhuri, Olik
• Application Number:
  US07/201,491
• Time in Patent Office: 509 Days
• Field of Search: 437/67, 437/69, 437/72, 437/73, 437/38
• US Class Current: 438/426
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence

Abstract

An isolation region is fabricated in a silicon substrate by first forming a silicon dioxide insulating layer on the substrate. A silicon nitride mask layer and an oxide layer are then deposited on the insulating layer. The oxide, mask and insulating layers and the substrate are etched to form a trench in the substrate. A channel stopper is implanted in substrate below the trench and the oxide layer is then stripped. Thereafter, the trench surface is oxidized to extend the insulating layer into the trench. Next, the trench is partially filled with polysilicon material, the surface of which is initially oxidized to extend the insulating layer over the trench. The mask layer is etched back to expose portions of the insulating layer adjacent the trench. The upper surface of the polysilicon material in the trench and portions of the substrate beneath exposed portions of the insulating layer are further oxidized to thicken the insulating layer over the trench.

Claims

1. A method for fabricating an isolation region in a semiconductor substrate comprising the steps of:

forming antiinsulating layer on said substrate;

forming a mask layer on said insulating layer;

forming a trench in said mask layer, said insulating layer and said substrate;

oxidizing an inner surface of said trench to extend said insulating layer into said trench;

filling a portion of said trench with semiconductor material;

initially oxidizing an upper surface of said semiconductor material to extend said insulating layer over said trench;

removing portions of said mask layer to expose portions of said insulating layer adjacent said trench; and

further oxidizing said upper surface of said semiconductor material and portions of said substrate adjacent said trench.

2. The method in accordance with claim 1 wherein said step of initially oxidizing an upper surface of said semiconductor material is halted when an upper surface of said insulating layer over said trench is approximately even with an upper surface of said insulating layer adjacent said trench.

3. The method in accordance with claim 1 wherein said step of initially oxidizing an upper surface of said semiconductor material is halted as an upper surface of said insulating layer over said trench rises above an upper surface of said insulating layer adjacent said trench.

4. The method in accordance with claim 1 wherein said trench is less than 2 microns wide.

5. The method in accordance with claim 4 wherein said trench is approximately 4-6 microns deep within said substrate.

6. The method in accordance with claim 1 wherein said step of forming a trench in said mask layer, said insulating layer and said substrate comprises the substeps of:

forming a second layer of insulating material on said mask layer;

etching the second layer of insulating material, the mask layer, the insulating layer and the substrate to form said trench; and

stripping said second layer from said mask layer.

7. The method in accordance with claim 6 wherein said second layer of insulating material comprises unannealed chemical vapor deposition oxide.

8. A method for fabricating an isolation region in a semiconductor substrate comprising the steps of:

forming an insulating layer on said substrate;

forming a mask layer on said insulating layer;

forming a trench extending through said mask and insulating layers and into said semiconductor substrate;

implanting dopant ions into said semiconductor substrate below said trench;

oxidizing an inner surface of said trench to extend said insulating layer into said trench;

filling a portion of said trench with semiconductor material;

initially oxidizing an upper surface of said semiconductor material in said trench to extend said insulating layer over said trench;

removing portions of said mask layer adjacent the oxidized surface of said semiconductor material to expose portions of said insulating layer adjacent said trench; and

further oxidizing said upper surface of said semiconductor material and portions of said substrate adjacent said trench.

9. The method in accordance with claim 8 wherein said step of initially oxidizing an upper surface of said semiconductor material is halted when an upper surface of said insulating layer over said trench is approximately even with an upper surface of said insulating layer adjacent said trench.

10. The method in accordance with claim 8 wherein said step of initially oxidizing an upper surface of said semiconductor material is halted as an upper surface of said insulating layer over said trench rises above an upper surface of said insulating layer adjacent said trench.

11. The method in accordance with claim 8 wherein said trench is less than 2 microns wide.

12. The method in accordance with claim 11 wherein said trench is 4-6 microns deep within said substrate.

13. The method in accordance with claim 8 wherein said step of forming a trench through said mask and insulating layers and into said substrate comprises the substeps of:

forming a second layer of insulating material on said mask layer;

etching the second layer of insulating material, the mask layer, the insulating layer and the substrate to form said trench; and

stripping said second layer from said mask layer.

14. The method in accordance with claim 13 wherein said second layer of insulating material comprises unannealed chemical vapor deposition oxide.

15. A method for fabricating an isolation region in a silicon substrate comprising the steps of:

forming a silicon dioxide insulating layer on said substrate;

forming a mask layer on said insulating layer;

forming an oxide layer on said mask layer;

etching the oxide layer, the mask layer, the insulating layer and the substrate to form a trench in said substrate;

stripping said oxide layer from said mask layer;

oxidizing an inner surface of said trench to extend said insulating layer into said trench;

filling a portion of said trench with polysilicon material;

initially oxidizing said polysilicon material to extend said insulating layer over said trench, oxidation of said polysilicon material continuing until an upper surface of said trench rises above an upper surface of said insulating layer adjacent said trench;

removing portions of said mask layer to expose portions of said insulating layer adjacent said trench; and

further oxidizing said upper surface of said polysilicon material and portions of said substrate adjacent said trench.

16. The method in accordance with claim 15 wherein said trench is less than 2 microns wide and is approximately 4-6 microns deep within said substrate.

17. The method in accordance with claim 15 wherein said oxide layer comprises unannealed chemical vapor deposition oxide.

18. The method in accordance with claim 17 further comprising the step of implanting dopant ions into said semiconductor substrate below said trench before the step of stripping said oxide layer from said mask layer.