Scanning method and apparatus for current signals having large dynamic range

• US 4,876,534 A
• Filed: 02/05/1988
• Issued: 10/24/1989
• Est. Priority Date: 02/05/1988
• Status: Expired due to Term

• Current Assignee: Foveon, Inc. (Avis Budget Group Incorporated)
• Original Assignee: Synaptics Incorporated
• Inventors: Allen, Timothy P., Mead, Carver A.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Pudpud, E. O.
• Application Number:
  US07/152,894
• Time in Patent Office: 627 Days
• Field of Search: 340/825.86, 340/825.95, 340/825.94, 340/825.79, 340/825.85, 358/213.11, 358/241, 358/212, 307/490-494, 307/580, 307/201, 250/578, 250/214 L, 330/257, 330/259, 357/30, 357/32
• US Class Current: 340/14.67
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

There is disclosed herein apparatus and a method for scanning information off a processing plane where the information is contained in a current signal having a very small amplitude and which can change signs and vary in amplitude by as much as five orders of magnitude. The preferred embodiment of the apparatus uses a pair of CMOS pass transistors connected to the individual processing elements and the row select lines. The pass transistors, when turned on, couple the output current from the processor containing the desired information to a column line. The column line is connected to a current to voltage converter in the form of a differential input amplifier having a non linear feedback circuit comprised of two diode connected CMOS transistors operating in the subthreshold region. The non linear feedback circuit provides an exponential transfer function which compresses the dynamic range of the output current from the processor to a smaller and more useable output range for an output voltage. The negative feedback to the inverting input coupled to the column line stabilizes the voltage on the column line to virtual ground thereby eliminating the delay associated with driving the parasitic capacitance of the column line with the very small output current from the processor in an attempt to substantially change the voltage of the column line.

Claims

1. An apparatus for reading a current signal from a source in an array of sources, each current having a changeable sign, a small amplitude and several orders of magnitude dynamic range comprising:

a first conductor;

a second conductor means for carrying a first addressing signal;

coupling means for coupling said current signal to said first conductor upon receipt of said first addressing signal;

an output node;

compression means having an input for coupling to a source of a reference voltage and coupled to said current signal only through said first conductor and coupled to said output node for converting said current signal to an output signal at said output node by a transfer function relating the voltage difference between the voltage at said output node and said reference voltage to said current signal such that said current signal increases faster than linearly in the positive direction for positive voltage differences and increases faster than linearly in the negative direction for negative voltage differences.

2. The apparatus of claim 1 wherein said compression means includes means having an exponential transfer function for causing the voltage difference between said output signal at said output node and a predetermined voltage to be approximately equal to the natural logarithm of said current signal.

3. The apparatus of claim 2 wherein said compression means comprises a transconductance differential input amplifier having an output, an inverting input and a non inverting input, and having said output coupled back to said inverting input through a non linear feedback network and further comprising a row conductor and isolation means having a control input for receiving an addressing signal and coupled between said output node to said row conductor for selectively coupling the signal at said output node to said row conductor upon receipt of said address signal.

4. The apparatus of claim 3 further comprising a first input for coupling to a first bias voltage source and a second input for coupling to a second bias voltage source, and wherein said non linear feedback network is comprised of a first MOS transistor of a first channel type having a drain terminal coupled to said first input and a source terminal coupled to said inverting input and a gate terminal coupled to said output of said amplifier and a second MOS transistor of a second channel type having a drain terminal coupled to said second input and having a source terminal coupled to said inverting input and having a gate terminal coupled to said output of said amplifier, and wherein said isolation means is a differential input amplifier having first and second differential inputs and an output, said first input coupled to said output node and said output coupled to both said row conductor and to said second input and having an enable input for receiving said address signal.

5. The apparatus of claim 4 wherein said transistors of said non linear feedback network operate in the subthreshold region.

6. The apparatus of claim 5 wherein said coupling means is comprised of a single MOS transistor having a first channel type and wherein said transconductance amplifier is comprised of a differential pair of MOS transistors with both transistors of said pair having the opposite channel type as said single MOS transistor of said coupling means

7. The apparatus of claim 5 wherein said coupling means is comprised of a first MOS transistor of a first channel type having its source terminal coupled to said current signal and its drain terminal coupled to said first conductor, and a second MOS transistor of a second channel type having its source terminal coupled to said first conductor and having its drain coupled to said current signal and wherein said first MOS transistor has its gate coupled to said first addressing signal and wherein said second MOS transistor has its gate terminal coupled to the inverse of said first addressing signal.

8. The apparatus of claim 1 wherein said compression means is a differential input amplifier having an inverting input coupled to said first conductor and having a non inverting input for coupling to a reference voltage source, and having an output, and further comprising a non linear feedback circuit coupled from said output to said inverting input wherein said current signal from said source in said array of sources is approximately equal to the current flowing through said non linear feedback circuit and further comprising a row conductor and isolation means coupled between said output node and said row conductor for selectively coupling the signal at said output node to said row conductor wherein said isolation means includes a pair of CMOS pass transistors each having a gate terminal coupled to receive an address signal and coupled between said output node and said row conductor so as to selectively couple the signal on said output node to said row conductor regardless of polarity of said signal when said address signals are in a predetermined state.

9. The apparatus of claim 3 wherein said non linear feedback network is comprised of a first MOS transistor of a first channel type having a drain terminal and a gate terminal both of which are coupled to said output and having a source terminal coupled to said inverting input, and a second MOS transistor of a second channel type having a drain terminal coupled to said source terminal of said first MOS transistor and having a gate and a source terminal coupled to said drain terminal of said first MOS transistor, both said first and second transistors being operated in the subthreshold region by virtue of the amplitude of said current signal.

10. The apparatus of claim 3 wherein said non linear feedback network is comprised of a first MOS transistor of a first channel type having drain, source and gate terminals and a second MOS transistor of a second channel type having drain, source and gate terminals, with the drain and source of said first and second MOS transistors, respectively, coupled to the output of said amplifier and the source and drain of said first and second MOS transistors, respectively, coupled to said inverting input of said amplifier, and the gate terminals of said first and second MOS transistors coupled to the inverting input of said amplifier, both said first and second transistors operating in the subthreshold region.

11. The apparatus of claim 3 wherein said non linear feedback network is comprised of a first MOS transistor having drain, source and gate terminals and a second MOS transistor of the same channel type as said first transistor and having drain, source and gate terminals, with the drain and source of said first and second MOS transistors, respectively, coupled to the output of said amplifier and the source and drain of said first and second MOS transistors, respectively, coupled to said inverting input of said amplifier, and wherein the gate terminal of one of said MOS transistors is coupled to said output of said amplifier and wherein the gate terminal of the other said MOS transistor is coupled to said inverting input of said amplifier.

12. An apparatus for reading information generated by a processor in an array of processing elements contained in a current signal generated by a processor, said current signal having a small amplitude and changeable sign and several orders of magnitude dynamic range, comprising:

a conductor shared by a plurality of said processing elements;

means having an input for a first addressing signal for coupling said current signal to said conductor upon receipt of said first addressing signal;

a differential input amplifier having an inverting input coupled to said current signal through said conductor and having a non inverting input for coupling to a reference voltage source and having an output; and

non linear feedback means coupled from said output to said inverting input of said amplifier for stabilizing the voltage on said conductor by negative feedback at a predetermined voltage and for causing the output voltage at said signal output to be within the operating limits of the amplifier for values of current flowing in said conductor having an amplitude varying by several orders of magnitude in either direction.

13. The apparatus of claim 12 wherein said amplifier is a transconductance differential amplifier having an output for presenting an output signal derived from said current signal, an inverting input coupled to said conductor and a non inverting input for coupling to a reference voltage.

14. The apparatus of claim 13 wherein said feedback means is comprised of a first diode having an anode terminal coupled to said output of said transconductance difference amplifier and its cathode coupled to the inverting input of said transconductance amplifier and a second diode having its anode terminal coupled to said inverting input of said amplifier and having its cathode coupled to the output of said amplifier.

15. The apparatus of claim 13 wherein said feedback means is comprised of a first MOS transistor of a first channel type having a gate terminal coupled to said output and having a drain terminal for coupling to a first reference potential and having a source terminal coupled to said inverting input, and a second MOS transistor of a second channel type having a source terminal coupled to said source terminal of said first MOS transistor and having a drain terminal coupled to said inverting input of said differential input amplifier and having a gate terminal coupled to said output of said differential input amplifier, both said first and second transistors being operated in the subthreshold region by virtue of the amplitude of said current signal.

16. The apparatus of claim 13 wherein said feedback means is comprised of a first input for coupling to a first bias voltage source and a second input for coupling to a second bias voltage source and further comprises a first MOS transistor of a first channel type having a drain terminal coupled to said first input and a source terminal coupled to said inverting input and a gate terminal coupled to said output of said amplifier and a second MOS transistor of a second channel type having a drain terminal coupled to said second input and having a source terminal coupled to said inverting input and having a gate terminal coupled to said output of said amplifier.

17. The apparatus of claim 16 further comprising a row conductor and an isolation means coupled between said output of said differential input amplifier and said row conductor and having an input for receiving an address signal for selectively coupling the signal at said output of said differential input amplifier to said row conductor when said address signal is in a predetermined state.

18. The apparatus of claim 17 wherein said isolation means is a differential input amplifier having first and second differential inputs and an output, said first input coupled to said output of said differential input amplifier and said output coupled to both said row conductor and to said second differential input and having an enable input for receiving said address signal.

19. An apparatus for reading a current signal having a changeable sign, a small amplitude and several orders of magnitude dynamic range comprising:

a first conductor;

a second conductor means for carrying a first addressing signal;

coupling means for coupling said current signal to said first conductor upon receipt of said first addressing signal using a single MOS transistor;

compression means coupled to said first conductor and having an input for receiving a second addressing signal for converting the current signal to an output signal in the form of a voltage difference across said compression means such that said current signal increases in the positive direction faster than linearly as a function of the voltage difference for positive voltage differences and increases in the negative direction faster than linearly for voltage differences which are negative.

20. The apparatus of claim 19 wherein said compression means comprises a differential input amplifier having inverting and non inverting differential inputs and having an output wherein said non inverting input is for coupling to a source of a reference voltage and further comprising a first input for coupling to a first bias voltage source and a second input for coupling to a second bias voltage source, and further comprising a first MOS transistor of a first channel type having a drain terminal coupled to said first input and a source terminal coupled to said inverting input and a gate terminal coupled to said output of said amplifier and a second MOS transistor of a second channel type having a drain terminal coupled to said second input and having a source terminal coupled to said inverting input and having a gate terminal coupled to said output of said amplifier.

21. The apparatus of claim 19 wherein said compression means comprises a differential input amplifier having inverting and non inverting differential inputs and having an output wherein said non inverting input is for coupling to a source of a reference voltage and further comprises a first MOS transistor of a first channel type having a drain terminal and a gate terminal both of which are coupled to said output and having a source terminal coupled to said inverting input, and a second MOS transistor of a second channel type having a drain terminal coupled to said source terminal of said first MOS transistor and having a gate and a source terminal coupled to said drain terminal of said first MOS transistor, both said first and second transistors being operated in the subthreshold region.

22. The apparatus of claim 19 wherein said compression means comprises a differential input amplifier having inverting and non inverting differential inputs and having an output wherein said non inverting input is for coupling to a source of a reference voltage and further comprises a first MOS transistor of a first channel type having drain, source and gate terminals and a second MOS transistor of a second channel type having drain, source and gate terminals, with the drain and source of said first and second MOS transistors, respectively, coupled to the output of said amplifier and the source and drain of said first and second MOS transistors, respectively, coupled to said inverting input of said amplifier, and the gate terminals of said first and second MOS transistors coupled to the inverting input of said amplifier, both said first and second transistors operating in the subthreshold region.

23. The apparatus of claim 19 wherein said compression means comprises a differential input amplifier having inverting and non inverting differential inputs and having an output wherein said non inverting input is for coupling to a source of a reference voltage and further comprises a first MOS transistor having drain, source and gate terminals and a second MOS transistor of the same channel type as said first transistor and having drain, source and gate terminals, with the drain and source of said first and second MOS transistors, respectively, coupled to the output of said amplifier and the source and drain of said first and second MOS transistors, respectively, coupled to said inverting input of said amplifier, and wherein the gate terminal of one of said MOS transistors is coupled to said output of said amplifier and wherein the gate terminal of the other said MOS transistor is coupled to said inverting input of said amplifier.

24. An apparatus for scanning an array of processing elements each of which generates an output current signal and for generating a plurality of output signals each of which corresponds to one said output current from one said processor of said array, comprising a plurality of scanning circuits, each said scanning circuit comprising:

a first conductor means shared by all the processing elements in a particular column of said array for carrying the output current signal of each processor in the particular column in a time multiplexed manner;

a second conductor means shared by all the processing elements in a particular row of said array for carrying a first addressing signal;

coupling means for coupling to said first conductor means upon receipt of said first addressing signal said output current signal from a corresponding one of said processing elements in the row of processing elements associated with the active first addressing signal;

compression means coupled to said first conductor means and shared by all the processing elements in said column and having an input for receiving a second addressing signal for, upon receipt of said second addressing signal, converting the output current signal coupled to said first conductor means to an output signal having a smaller dynamic range than the dynamic range of said output current signal regardless of the sign of said current signal;

row addressing means for sequentially activating each said first addressing signal for a time sufficient to allow all the processing elements in the appropriate row to have their output current signals read by the appropriate ones of said scanning circuits; and

column addressing means for sequentially activating each said second addressing signal during the time during which any particular first addressing signal is active, each said second addressing signal being activated for a sufficiently long time to allow the conversion of the output current signal from the processor in the selected row and column to be converted to a corresponding one of said plurality of said output signals, and for repeating this process for the activations of all said first row addressing signals.

25. The apparatus of claim 24 wherein said compression means comprises a differential input amplifier having inverting and non inverting differential inputs and having an output wherein said non inverting input is for coupling to a source of a reference voltage and further comprising a first input for coupling to a first bias voltage source and a second input for coupling to a second bias voltage source, and further comprising a first MOS transistor of a first channel type having a drain terminal coupled to said firs input and a source terminal coupled to said inverting input and a gate terminal coupled to said output of said amplifier and a second MOS transistor of a second channel type having a drain terminal coupled to said second input and having a source terminal coupled to said inverting input and having a gate terminal coupled to said output of said amplifier.

26. The apparatus of claim 24 wherein said compression means comprises a differential input amplifier having inverting and non inverting differential inputs and having an output wherein said non inverting input is for coupling to a source of a reference voltage and further comprises a first MOS transistor of a first channel type having a drain terminal and a gate terminal both of which are coupled to said output and having a source terminal coupled to said inverting input, and a second MOS transistor of a second channel type having a drain terminal coupled to said source terminal of said first MOS transistor and having a gate and a source terminal coupled to said drain terminal of said first MOS transistor, both said first and second transistors being operated in the subthreshold region

27. The apparatus of claim 24 wherein said compression means comprises a differential input amplifier having inverting and non inverting differential inputs and having an output wherein said non inverting input is for coupling to a source of a reference voltage and further comprises a first MOS transistor of a first channel type having drain, source and gate terminals and a second MOS transistor of a second channel type having drain, source and gate terminals, with the drain and source of said first and second MOS transistors, respectively, coupled to the output of said amplifier and the source and drain of said first and second MOS transistors, respectively, coupled to said inverting input of said amplifier, and the gate terminals of said first and second MOS transistors coupled to the inverting input of said amplifier, both said first and second transistors operating in the subthreshold region.

28. The apparatus of claim 24 wherein said compression means comprises a differential input amplifier having inverting and non inverting differential inputs and having an output wherein said non inverting input is for coupling to a source of a reference voltage and further comprises a first MOS transistor having drain, source and gate terminals and a second MOS transistor of the same channel type as said first transistor and having drain, source and gate terminals, with the drain and source of said first and second MOS transistors, respectively, coupled to the output of said amplifier and the source and drain of said first and second MOS transistors, respectively, coupled to said inverting input of said amplifier, and wherein the gate terminal of one of said MOS transistors is coupled to said output of said amplifier and wherein the gate terminal of the other said MOS transistor is coupled to said inverting input of said amplifier.

29. An apparatus for scanning an array of processing elements arranged in rows and columns, each of said processors generating a current signal and for generating a plurality of output signals each of which corresponds to one said output current from one said processor of said array, comprising a plurality of column scanning circuits, each said column scanning circuit comprising:

a first conductor means shared by all the processing elements in a particular column of said array for carrying the output current signal of each processor in the particular column in a time multiplexed manner;

coupling means for each said processor in each row of said array, each said coupling means having an input for receiving a first addressing signal, for coupling said current signal output by the processing element associated with each said coupling means to said first conductor means upon activation of a predetermined state of said first addressing signal;

a differential input amplifier shared by all the processing elements in a column of said array and having an inverting input coupled to said first conductor means and having a non inverting input for coupling to a reference voltage source and having an output at which output signals corresponding to the processing elements in the column associated with said first conductor means appear; and

feedback means shared by all the processing elements in a column of said array and coupled from said output to said inverting input of said amplifier for stabilizing the voltage on said first conductor means by negative feedback at a predetermined voltage and for causing the difference voltage between the output voltage at said output and the voltage at said non inverting input to be proportional to the natural logarithm of the signal current flowing in said first conductor means;

an output conductor associated with and shared by all the column scanning circuits of said array;

isolation means coupled between said output of said differential input amplifier and said output conductor and having an input for receiving a second addressing signal for selectively coupling the signal at said output to said output conductor when said second addressing signal is in a predetermined state;

and said apparatus for scanning the array further comprising;

row and column addressing means for sequentially activating a predetermined state of each of said first and second addressing signals in such a manner so as to read all the current signals of all or some defined portion the processing elements of said array.

30. The apparatus of claim 29 further comprising a row conductor and a first input for coupling to a first bias voltage source and a second input for coupling to a second bias voltage source, and wherein said feedback means is comprised of a first MOS transistor of a first channel type having a drain terminal coupled to said first input and a source terminal coupled to said inverting input and a gate terminal coupled to said output of said amplifier and a second MOS transistor of a second channel type having a drain terminal coupled to said second input and having a source terminal coupled to said inverting input and having a gate terminal coupled to said output of said amplifier, and wherein said isolation means is a second differential input amplifier having first and second differential inputs and an output, said first differential input coupled to said output node of said differential input amplifier and said output coupled to both said row conductor and to said second differential input of said second differential input amplifier, and said second differential input amplifier having an enable input for receiving said second addressing signal.

31. The apparatus of claim 29 wherein said feedback means is comprised of a first MOS transistor of a first channel type having a drain terminal and a gate terminal both of which are coupled to said output and having a source terminal coupled to said inverting input of said differential input amplifier, and a second MOS transistor of a second channel type having a drain terminal coupled to said source terminal of said first MOS transistor and having a gate and a source terminal coupled to said drain terminal of said first MOS transistor, both said first and second transistors being operated in the subthreshold region by virtue of the amplitude of said current signal.

32. The apparatus of claim 29 wherein said feedback means is comprised of a first MOS transistor of a first channel type having drain, source and gate terminals and a second MOS transistor of a second channel type having drain, source and gate terminals, with the drain and source of said first and second MOS transistors, respectively, coupled to the output of said differential input amplifier and the source and drain of said first and second MOS transistors, respectively, coupled to said inverting input of said differential input amplifier, and the gate terminals of said first and second MOS transistors coupled to the inverting input of said differential input amplifier, both said first and second transistors operating in the subthreshold region.

33. The apparatus of claim 33 wherein said feedback means is comprised of a first MOS transistor having drain, source and gate terminals and a second MOS transistor of the same channel type as said first transistor and having drain, source and gate terminals, with the drain and source of said first and second MOS transistors, respectively, coupled to the output of said differential input amplifier and the source and drain of said first and second MOS transistors, respectively, coupled to said inverting input of said differential input amplifier, and wherein the gate terminal of one of said MOS transistors is coupled to said output of said amplifier and wherein the gate terminal of the other said MOS transistor is coupled to said inverting input of said amplifier.