Digital map system

• US 4,876,651 A
• Filed: 05/11/1988
• Issued: 10/24/1989
• Est. Priority Date: 05/11/1988
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Thompson, Eldon J., Dawson, John F., Cousens, James A.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Trans, V. N.
• Application Number:
  US07/192,798
• Time in Patent Office: 531 Days
• Field of Search: 364/443, 364/449, 364/460, 364/518, 364/521, 364/522, 364/200, 364/900, 434/2, 434/3, 342/13, 342/192, 342/179, 340/995, 340/723, 340/798
• US Class Current: 701/200
• CPC Class Codes: G01C 21/20 Instruments for performing navigational calculations G01C21/24, G01C21/26 take precedence
• CPC Class Codes: G09B 29/106 using electronic means

Abstract

A digital mapping display system for an aircraft wherein map data from a mass memory unit is periodically loaded into RAM in the form of a cache memory in accordance with the aircraft trajectory. The cache memory is randomly addressable within the physical address space of a control processor, individual segments of the cache memory being loaded with map data and updated while other segments are being displayed, thereby avoiding the inherent delay of accessing the mass memory unit and addressing the entire RAM array. Parallel processing of map data and symbology facilitate a real-time display.

Claims

1. Digital mapping display system for an aircraft, wherein said aircraft includes a mission computer for generating digital signals indicative of the aircraft'"'"'s present longitude and latitude coordinate positions, a heading signal indicative of the angular direction of motion, and signals corresponding to map data and graphical data, further including a mass memory unit for storing said map data signals in digital form representative of a map of territory overflown by the aircraft and for providing map data signals corresponding thereto, and for storing overlay data in digital form representative of graphical information to be superimposed on said map data, and for providing overlay data signals corresponding thereto, said display system comprising:

mass data controller means for extracting said map data signals or said overlay data signals from said mass memory unit and periodically providing updated images,

cache memory means coupled to said mass data controller means for electronically storing digital data indicative of a portion of a complete map of territory overflown by and surrounding said aircraft, said cache memory means comprised of an array of storage segments, the number of said storage segments being substantially less than the number of segments necessary to store an image representative of a complete map of territory and greater than that necessary to store an image of said portion of a complete map for any orientation of said aircraft, each such segment being randomly positionally programmable along predetermined X and Y coordinates corresponding to latitude and longitude of said complete map of territory, and responsive to means for dynamically relocating said positions in a predetermined physical address space with respect to changes in said aircraft'"'"'s coordinate position and orientation, said storage segments configured in a logical Cartesian coordinate array corresponding to said portion of said complete map of territory, each of said segments comprised of a plurality of storage elements wherein each of said storage elements stores at least one bit of digital map data and wherein each storage location has a corresponding address, and further comprising segment mapping means responsive to an address command for storing an address representative of the location of each segment within said physical address space and the location of each storage element within each segment,

first control processor means responsive to said signals generated by said mission computer and for transmitting status signals to said mission computer, and further providing display mode commands and mass memory control data,

second control processor means responsive to said first control processor means for retrieving said map and data overlay signals from said mass memory unit in accordance with said aircraft'"'"'s coordinate position, for providing control signals for periodically storing said updated images derived from said mass memory unit into said cache memory means, and for controlling data display,

address generator means responsive to control signals from said second control processor means for reading and extracting map data or overlay data from said cache memory means, and transferring said data in the form of displayable pixels to first or second memory means,

video generator means, responsive to digital outputs of said first and second memory means, for converting said map data pixel signal and said overlay data pixel signal to signals displayable in color or monochrome form, and

display means coupled to said video generator means and responsive to said map data and overlay data pixel signals and to a source of timing signals for providing a displayable image at a predetermined frame rate, said image corresponding to at least said portion of said complete map of territory.

30. A digital map system as set forth in claim 1, said mass data controller means further comprising:

fiber optic interface means coupled to said mass memory unit for receiving optical signals in digital form and converting said optical signals to electrical signals in serial form, and

disk controller means responsive to said serial electrical signals, for converting said signals to parallel form and providing said converted signals to said cache memory means,

said disk controller means further responsive to said second control processor means for initiating a block transfer of data from said memory unit controller means to said cache memory means.

31. A digital mapping display system as set forth in claim 30 said source of timing signals comprising:

timing generator means responsive to control signals from said first control processor means for providing x_i, y_j addresses to said first and second memory means for reading said pixel signals in sequential order corresponding to a predetermined frame rate and video resolution, and for providing horizontal and vertical synchronizing signals, horizontal and vertical blanking signals, pixel clock and line video timing signals.

32. A digital mapping system as set forth in claim 31, wherein said timing generator means has a scan pattern comprising:

two interlaced fields of map or overlay data,

means for generating sequential addresses along every other parallel line beginning with said first starting addresses to generate said first field of data and to generate sequential addresses along the parallel lines between said very other parallel line beginning with said second starting addresses to generate said second field of data interlaced with said first field of data,

means synchronous with said vertical synchronization signal for generating a ping-pong memory select signal for alternately and sequentially selecting one of said first or second memory banks and one of said third or fourth memory bans, for reading one of said first or second memory bans and writing into one other than said one of said first or second memory banks, and reading one of said third or forth memory banks and writing into one other than said one of said third or fourth memory bans.

33. A digital mapping system as set forth in claim 32, wherein said means for generating a ping-pong select signal is synchronous with a predetermined video frame rate, and said video frame rate is comprised of three fields comprised of sequentially addressing said first and second fields of data.

34. A digital map system as set forth in claim 33, said cache memory means further comprising:

a plurality of address selector switch means responsive to signals from said address generator means, said second control processor means, and said mass data controller means, for selectively addressing one of a plurality of said storage segments,

first buffer means, responsive to map data signals from said plurality of storage segments, for selectively providing an output from one of said storage segments to said video processor means,

second buffer means responsive to overlay data signals from said plurality of storage segments for selectively providing an output from one of said storage segments to said overlay processor means, and

third buffer means, responsive to decoded data signals from said mass data controller means for selectively providing map and overlay data to be stored in said plurality of storage segments of said cache memory means, and

segment controller means comprising means coupled to receive address signals from said address generator means and address and data signals from said second control processor means, and means for selectively enabling said first, second, or third buffer means for loading data from a first data bus coupled to said mass data controller means into said storage segments and for loading stored data into a second data bus coupled to said video processor means,

so that ones of said storage segments can be loaded with map or overlay data while still further ones of said storage segments can be simultaneously read into said first or second scene memories, whereby said scene memories can be loaded without contemporaneous access of said mass memory unit.

35. A digital map display system as set forth in claim 34 further comprising a display list register for storing an address wherein associated overlay data is stored in at least one of said parallel planes.

2. The apparatus as set forth in claim 2, said cache memory means further comprising means for storing graphical images for overlaying said portions wherein ones of said storage elements store at least one bit of overlay data.

3. A digital mapping display system as set forth in claim 2, wherein said cache memory means further comprises:

an n×

m array of buffer segments, each buffer segment being independently programmable with respect to its logical position within said physical X, Y coordinate space to form a predetermined virtual image plane, wherein each said buffer segment is addressable by its physical position in accordance with an x_i, y_j coordinate position and by a logical position within a virtual image plane.

4. A digital mapping display system as set forth in claim 3, wherein said segment mapping means comprises an associated mapping register programmable by said second control processor means and having a two-dimensional address for defining where an associated buffer segment is located within said physical address space and to which address said segment will respond, whereby ones of said segments may be mapped anywhere within said physical address space by programming said associated register.

5. A digital mapping display system as set forth in claim 4, wherein said digital data is transferred to said buffer segments at least one segment at a time and a segment of data bits to update said first or second memory means is sequentially scanned over a plurality of said segments logically organized contiguously in accordance with said physical address space, but not necessarily contiguously within said n×

m array.

6. A digital mapping display system as set forth in claim 5, wherein said digital data is transferred from said mass memory unit to said buffer segments for updating said cache memory means and a predetermined plurality of said buffer segments are configured in a single memory plane.

7. A digital mapping display system as set forth in claim 6 wherein said plurality of buffer segments are configured in a plurality of parallel image planes having corresponding storage elements in each plane and wherein said corresponding storage elements in each plane have the same address for collectively storing a digital word representative of color and intensity of a displayed pixel, and wherein said video generator means further comprises decoder means responsive to said digital word when stored in said first or second memory means and to said pixel clock and line video timing signals for generating analog pixel signals in accordance therewith.

8. A digital map system as set forth in claim 7, further comprising video processor means, comprising:

linear feature generator means responsive to address and data signals from said overlay processor means representative of displayable locations in said second memory means for selectively providing linear feature signals of predetermined color value,

sun angle shading generator means, responsive to control and data signals from said cache memory means for selecting a predetermined reflectivity map and providing a predetermined value of color intensity at a given elevation corresponding to predetermined values of sun azimuth, sun zenith and aircraft heading,

color band storage means responsive to terrain elevation values and to displayable locations for providing color hues defining bands of a predetermined color at a given range of elevations, and further responsive to aircraft altitude for providing further color hues representative of differences in elevation of the terrain and the aircraft altitude,

means for combining said hues in said color bands or said further hues with values of color intensity at a corresponding elevation and displayable location to derive modified color values in primary color format,

means responsive to said modified color values and to elevation differences of an integer x_i, y_j location and a non-integer x, y location at said displayable location for deriving a color composite in primary color value form,

means responsive to said elevation differences for deriving an average value thereof, means for comparing said average elevation value with a table of predetermined elevation values, and means for providing a resultant color value output corresponding to a predetermined elevation when at least one pair of said compared values coincide, said output corresponding to a change in elevation value, and

means for selectively applying said color composite and said resultant color value to derive a limited range of color values corresponding to neighboring elevations and for applying the selected color value to said second memory means.

9. A digital map system as set forth in claim 8 wherein said video processor means further comprises means responsive to control signals from said first control processor means for displaying a contour line corresponding to said resultant color value at a plurality of neighboring locations at a predetermined elevation and for blanking a signal corresponding to said color composite when said non-integer x, y coordinate location coincides with said predetermined elevation, and for blanking said contour line and displaying said color composite when said non-integer location and said given elevation value do not coincide.

10. A digital map system as set forth in claim 9 wherein said linear feature generator means further comprises:

code book means for storing linear feature data in digital form, said code book means comprised of a plurality of addressable storage locations wherein each of said storage locations stores one bit of digital data, and coupled to said overlay processor means for receiving linear feature data therefrom for storage within, wherein said stored data is responsive to updating of said cache memory means by said mass memory data controller means, said stored data representative of a plurality of selectable linear features and responsive to command signals from said overlay processor means for selecting predetermined ones of said linear features,

first switch means responsive to command signals from said cache memory means for selecting ones of said predetermined linear features in accordance with corresponding ones of said storage segments of said cache memory means, and further responsive to command signals for selecting predetermined groups of said predetermined linear features,

second switch means responsive to said command signals from said first control processor means for selectively enabling or disabling ones of said linear features, and

linear feature storage means coupled to receive said selected linear features and color command signals from said first control processor means for providing a linear feature color output signal to said first memory means.

11. A digital map system as set forth in claim 10 wherein said address generator means further comprises:

decoder means responsive to address signals from said second control processor means for selectively providing initialization commands,

x read address generator means, responsive to command signals from said decoder means, data signals from said second control processor means, and to a source of sequential control signals for providing an read address signal corresponding to a plurality of sequential x coordinate pixel locations,

y read address generator means, responsive to said command signals from said decoder means and to said data signals from said second control processor means for providing a y read address signal corresponding to a plurality of sequential y coordinate pixel locations,

means for reading said x, y read address signals into said cache memory means and deriving pixel signals therefrom representative of said map data or overlay data,

means responsive to said command, control, and data signals for generating an x write address corresponding to said x read address,

means responsive to said command, control, and data signals for generating a y write address corresponding to said y read address,

line counter means for generating sequential status signals corresponding to completion of an x count representative of a predetermined number of pixels in the x-coordinate direction and completion of a y count corresponding to a predetermined number of pixels in the y-coordinate direction, the completion of said x and y counts corresponding to a frame of data, and

state sequencer means for generating said x and y read and write control signals and for providing further control signals to said cache memory means, said overlay processor means, said video processor means, and said first memory means.

12. A digital map system as set forth in claim 11, further comprising graphics generator mean coupled to receive overlay data in vector form from said overlay processor means and to provide feature symbology and x_i, y_j coordinate addresses corresponding thereto to said second memory means.

13. A digital map system as set forth in claim 12, wherein said graphics generator means further comprises:

I/O control means responsive to digital signals from said overlay processor means, said digital signals representative of a desired graphical symbol to be presented on said display means,

digital memory means coupled to said I/O control means for storing graphical images in digital form corresponding to a plurality of displayable symbols,

processor means responsive to said digital memory means for converting said stored images to a plurality of vector instructions,

geometric conversion means coupled to receive said vector instructions for translating said vector instructions into incremental displacement commands representative of incremental steps along said X and Y coordinate axes and of a predetermined length,

X accumulator means for providing a digital output corresponding to a sum of said incremental steps along said X coordinate axis so as to incrementally change said digital output to provide a substantially linear X deflection signal,

Y accumulator means for providing a further digital output corresponding to a sum of said incremental steps along said Y coordinate axis so as to incrementally change said further digital output to provide a substantially linear Y deflection signal, and

video control means responsive to said I/O control means for controlling the displayed color of pixels corresponding to said X and Y deflection signals.

14. The graphics generator means as set forth in claim 13, wherein one of said incremental displacement commands is representative of a polar vector.

15. The graphics generator means as set forth in claim 14, wherein one of said incremental displacement commands is representative of a tangent vector.

16. The graphics generator means as set forth in claim 15, wherein one of said incremental displacement commands is representative of a rectangular vector.

17. The graphics generator means as set forth in claim 16, further comprising means for rotating said polar vector or said rectangular vector by a predetermined angular displacement.

18. The graphics generator means as set forth in claim 17, further comprising means for controlling the number of said incremental steps in accordance with said angular displacement and a vector length signal.

19. The graphics generator as set forth in claim 18, wherein said digital memory means is sequentially responsive to said I/O control means for writing images in digital form therein and to said processor means for reading out said images.

20. A digital map system as set forth in claim 19, said first memory means comprising:

first and second alternately sequenced memory banks for storing first and second frames of image signals respectively, and

switching means, responsive to digital signals synchronous with said timing generator means for alternately;

(A) controlling said first sequenced memory bank for writing updated image signals into said first sequenced memory bank with respect to said first frame of image signals while controlling said second sequenced memory bank for reading out said second frame to said display system and

(B) controlling said second sequenced memory bank for writing updated image signals into said second sequenced memory bank with respect to said second frame while controlling said first sequenced memory bank for reading out said updated image.

21. A digital map system as set forth in claim 20 said first memory means further comprising:

control register means responsive to signals from said first control processor means, said source of timing signals, said address generator means and said video processor means, for generating a memory address command and a data write command and for providing video processor data signals for writing into said first and second alternately sequenced memory banks,

said switching means further comprising;

(A) first multiplexer means selectively responsive to a first signal from said address generator means corresponding to an address in said cache memory means and to a second signal from said source of timing signals corresponding to an address in said video generator means and coupled to said control register means for providing one of said first or second address signals to said first alternately sequenced memory bank,

(B) second multiplexer means selectively responsive to a third signal corresponding to a further address in said cache memory means from said address generator means and a fourth signal from said source of timing signals corresponding to a further address in said video generator means coupled to said control register means for providing one of said third or fourth address signals to said second alternately sequenced memory bank, and

(C) third multiplexer means for receiving data stored in said first and second alternately sequenced memory banks in response to a control signal from said control register means and providing a data signal corresponding to a selected one of said sequenced memory banks to said video generator means in response to a control signal from said control register means,

wherein said control register means is operative to read in a first memory address command from said address generator means and store video processor data in a first one of said alternately sequenced memory banks while reading in a first memory address command from said source of timing signals to a second one of said alternately sequenced memory banks and reading out data stored therein to said video generator means and then reading in a second sequential memory address command from said source of timing signals to said first one of said alternately sequenced memory banks and reading out the data previously stored therein to said video generator means while reading in a second sequential memory address command from said address generator means and storing video processor data corresponding thereto into said second one of said alternately sequenced memory banks, so that said first and second alternately sequenced memory banks are caused to read in data and write out data in ping-pong fashion, one of said alternately sequenced memory banks being loaded with new video processor data while the other of said alternately said sequenced memory banks reads out its data into said video generator means.

22. A digital mapping display system as set forth in claim 21, said first memory means further comprising means for alternately and sequentially storing map data in said first bank while map data stored in said second bank is read out for said display, and for storing updated map data in said second bank while map data stored in said first bank is read out, said reading and writing operations responsive to control signals from said first control processor means and to said switching means for providing a pixel signal output corresponding to said map data,

said second memory means further comprising third and fourth memory banks for alternately and sequentially storing overlay data in said third bank thereof while overlay data in said fourth bank thereof is read out for said display, and for storing updated overlay data in said fourth bank while overlay data stored in said third bank thereof is read out, said reading and writing operations responsive to further control signals from said first control processor means and to said switching means, for providing a pixel signal corresponding to said overlay data.

23. A digital map system as set forth in claim 22 wherein said video generator means further comprises:

means for converting a map data pixel signal to a first primary color signal in analog form and

means for converting an overlay data pixel signal to a second primary color signal in analog form.

24. A digital map system as set forth in claim 23, wherein said video generator means further comprises:

means for converting said map data pixel signal or said overlay data pixel signal to a monochrome signal in analog form, and

means for selectively outputting said first or second primary color signals or said monochrome signal.

25. A digital map system as set forth in claim 24, said video generator means further comprising:

first lookup table storage means for receiving at least a four bit digital word and providing an eight bit color word in digital form corresponding to a predetermined primary color value.

26. A digital map system as set forth in claim 25, said video generator means further comprising

second lookup table storage means for receiving at least a four bit digital word and providing an eight bit word in digital form corresponding to a predetermined monochrome value.

27. A digital map system as set forth in claim 26, said video generator means further comprising means responsive to said first control processor means for loading color values into at least two of said look-up table storage means simultaneously.

28. A digital map system as set forth in claim 26, wherein said video generator means further comprises means for providing an analog video signal in RS-170A format.

29. A digital map system as set forth in claim 27, said video generator means further comprising means for providing a composite sync signal and combining said composite sync signal with a predetermined one of said signals in analog form.

36. A method for generating a digital mapping display system for an aircraft, wherein said aircraft includes a mission computer for generating digital signals indicative of the aircraft'"'"'s present longitude and latitude coordinate positions, a heading signal indicative of the angular direction of motion, and signals corresponding to map data and graphical data, further including a mass memory for storing said map data signals in digital form representative of a map of territory overflown by the aircraft and for providing map data signals corresponding thereto, and for storing overlay data in digital form representative of graphical information to be superimposed on said map data, and for providing overlay data signals corresponding thereto, said display system comprising the steps of:

extracting said map data signals or said overlay data signals from said mass memory unit and periodically providing updated images,

storing digital images indicative of a portion of a complete map of territory overflown by and surrounding said aircraft in a cache memory means, said cache memory means comprised of an array of storage segments, the number of said storage segments being substantially less than the number of segments necessary to store an image representative of a complete map of territory and greater than that necessary to store an image of said portion of a complete map for any orientation of said aircraft, each such segment being randomly positionally programmable along predetermined X and Y coordinates corresponding to latitude and longitude of said complete map of territory;

dynamically relocating said positions in a predetermined physical address space with respect to changes in said aircraft'"'"'s coordinate position and orientation;

configuring said storage segments in a logical Cartesian coordinate array corresponding to said portion of said complete map of territory, each of said segments comprised of a plurality of storage elements wherein each of said storage elements stores at least one bit of digital map data and wherein each storage location has a corresponding address; and

said segment means in mapping response to an address command for storing an address representative of the location of each segment within said physical address space and the location of each storage element within each segment,

transmitting status signals to said mission computer, and further providing display mode commands and mass memory control data, in response to signals generated by said mission computer,

retrieving said map and data overlay signals from said mass memory unit in accordance with said aircraft'"'"'s coordinate position, for providing control signals for periodically storing said updated images derived from said mass memory unit into said cache memory means, and for controlling data display,

generating address signals for reading and extracting map data or overlay data from said cache memory means, and transferring said data in the form of displayable pixels to first or second memory means,

generating video signals by converting said map data pixel signals and said overlay data pixel signals to signals displayable in color or monochrome form, and

applying said converted map data and overlay data pixel signals and a source of timing signals to a display for providing a displayable image at a predetermined frame rate, said image corresponding to at least said portion of said complete map of territory.

37. The method as set forth in claim 36, said step of storing digital images further comprising storing graphical images for overlaying said portions wherein ones of said storage elements store at least one bit of overlay data.

38. The method as set forth in claim 37, wherein said cache memory means further comprises an n×

m array of buffer segments, each buffer segment being independently programmable with respect to its logical position within said physical X, Y coordinate space to form a predetermined logical image plane, and wherein the step of storing an address in each said segment includes a physical position in accordance with an x_i, y_j coordinate position and a logical position within a virtual image plane.

39. The method as set forth in claim 38, wherein said segment mapping means comprises an associated mapping register programmable by said second control processor means and having a two-dimensional address for defining where an associated buffer segment is located within said physical address space and to which address said segment will respond, wherein the step of mapping said segments provides for mapping anywhere within said physical address space by programming said associated register.

40. The method as set forth in claim 39, further including the step of transferring digital data to said buffer segments at least one segment at a time and a sequentially scanning a segment of data bits to update said first or second memory means over a plurality of said segments logically organized contiguously in accordance with said physical address space, but not necessarily contiguously within said n×

m array.

41. The method as set forth in claim 40, further including the step of transferring said digital data from said mass memory unit to said buffer segments for updating said cache memory means and configuring a predetermined plurality of said buffer segments in a single memory plane.

42. The method as set forth in claim 41 further including the steps of configuring said plurality of buffer segments in a plurality of parallel image planes having corresponding storage elements in each plane and collectively storing a digital word representative of color and intensity of a displayed pixel in corresponding storage elements in each plane having the same address, and further generating analog pixel signals by said video generator means in response to said digital word when stored in said first or second memory means and to said pixel clock and line video timing signals applied to decoder means.

43. The method as set forth in claim 42, including the steps of:

selectively providing linear feature signals of predetermined color value by applying, address and data signals from said overlay processor means representative of displayable locations in said second memory means to linear feature generation means,

applying control and data signals from said cache memory means to sun angle shading generator means for selecting a predetermined reflectivity map and providing a predetermined value of color intensity at a given elevation corresponding to predetermined values of sun azimuth, sun zenith and aircraft heading,

applying terrain elevation values and displayable locations for providing color hues defining bands of a predetermined color at a given range of elevations, to color band generator means and further applying an aircraft altitude signal for providing further color hues representative of differences in elevation of the terrain and the aircraft altitude,

combining said hues in said color bands or said further hues with values of color intensity at a corresponding elevation and displayable location to derive modified color values in primary color format,

applying said modified color values and elevation differences of an integer x_i, y_j location and a non-integer x, y location at said displayable location to derive a color composite in primary color value form,

applying said elevation differences to derive an average value thereof, comparing said average elevation value with a table of predetermined elevation values, and providing a resultant color value output corresponding to a predetermined elevation when at least one pair of said compared values coincide, said output corresponding to a change in elevation value, and

selectively applying said color composite and said resultant color value to derive a limited range of color values corresponding to neighboring elevations and applying the selected color value to said second memory means.

44. The method as set forth in claim 43 for further comprising the steps of displaying a contour line corresponding to said resultant color value at a plurality of neighboring locations at a predetermined elevation, blanking a signal corresponding to said color composite when said non-integer x, y coordinate location coincides with said predetermined elevation, and blanking said contour line and displaying said color composite when said non-integer location and said given elevation value do not coincide.

45. A digital map system as set forth in claim 44 further including the step of storing linear feature data in a code book in digital form in a third memory, said code book comprised of a plurality of addressable storage locations wherein each of said storage locations stores one bit of digital data, and applying linear feature data for storage within said third memory, wherein said stored data is responsive to updating of said cache memory means by said mass memory data controller means, said stored data representative of a plurality of selectable linear features and responsive to command signals from said overlay processor means for selecting predetermined ones of said linear features,

applying command signals from said cache memory means to first switch means for selecting ones of said predetermined linear features in accordance with corresponding ones of said storage segments of said cache memory means, and applying command signals for selecting predetermined groups of said predetermined linear features,

applying command signals to second switch means for selectively enabling or disabling ones of said linear features, and

applying selected linear features and color command signals to a fourth memmory for providing a linear feature color output signal to said first memory means.

46. The method as set forth in claim 45 further comprising the steps of applying address signals for selectively providing initialization commands to address generator decoder means,

applying command signals from said decoder means, data signals, and a source of sequential control signals to x read address generator means for providing an x read address signal corresponding to a plurality of sequential x coordinate pixel locations,

applying command signals from said decoder means and data signals to y read address generator means for providing a y read address signal corresponding to a plurality of sequential y coordinate pixel locations,

reading said x, y read address signals into said cache memory means and deriving pixel signals therefrom representative of said map data or overlay data,

generating an x write address in response to said command, control, and data signals corresponding to said x read address,

generating a y write address in response to said command, control, and data signals corresponding to said y read address,

applying a line counter for generating sequential status signals corresponding to completion of an x count representative of a predetermined number of pixels in the x-coordinate direction and completion, of a y count corresponding to a predetermined number of pixels in the y-coordinate direction, the completion of said x and y counts corresponding to a frame of data, and

generating said x and y read and write control signals and providing further control signals to said cache memory means, said overlay processor means, said video processor means, and said first memory means.

47. The method as set forth in claim 46, further comprising the steps of applying overlay data in vector form and providing feature symbology and x_i, y_j coordinate addresses corresponding thereto to said second memory means from graphics generator means.

48. The method as set forth in claim 47, wherein the steps of applying overlay data, feature symbology, and coordinate addresses to said graphics generator means further comprises:

applying digital signals to I/O control means, said digital signals representative of a desired graphical symbol to be presented on said display means,

storing graphical images in digital form corresponding to a plurality of displayable symbols in digital memory means,

converting said stored images to a plurality of vector instructions,

translating said vector instructions into incremental displacement commands representative of incremental steps along said X and Y coordinate axes and of a predetermined length,

providing a digital output corresponding to a sum of said incremental steps along said X coordinate axis so as to incrementally change said digital output to provide a substantially linear X deflection signal,

providing a further digital output corresponding to a sum of said incremental steps along said Y coordinate axis so as to incrementally change said further digital output to provide a substantially linear Y deflection signal, and

controlling the displayed color of pixels corresponding to said X and Y deflection signals.

49. The method as set forth in claim 48, wherein the step of providing one of said incremental displacement commands is representative of providing a polar vector.

50. The method as set forth in claim 49, wherein the step of providing one of said incremental displacement commands is representative of providing a tangent vector.

51. The method as set forth in claim 50, wherein the step of providing one of said incremental displacement commands is representative of providing a rectangular vector.

52. The method as set forth in claim 51, further comprising the step of rotating said polar vector or said rectangular vector by a predetermined angular displacement.

53. The method as set forth in claim 52, further comprising the step of controlling the number of said incremental steps in accordance with said angular displacement and a vector length signal.

54. The method as set forth in claim 53, further comprising the steps of sequentially writing images in digital form into said digital memory means for reading out said images.

55. The method as set forth in claim 54, further comprising:

storing first and second frames of image signals respectively, in first and second alternately sequenced memory banks of said first memory means, and

switching digital signals synchronous with said timing generator means for alternately;

(A) controlling said first sequenced memory bank for writing updated image signals into said first sequenced memory bank with respect to said first frame of image signals while controlling said second sequenced memory bank for reading out said second frame to said display system and

(B) controlling said second sequenced memory bank for writing updated image signals into said second sequenced memory bank with respect to said second frame while controlling said first sequenced memory bank for reading out said updated image.

56. The method as set forth in claim 55 further comprising:

the steps of generating a memory address command and a data write command and providing video processor data signals for writing into said first and second alternately sequenced memory banks,

(A) selectively applying a first signal from said address generator means corresponding to an address in said cache memory means and a second signal from said source of timing signals corresponding to an address in said video generator means and coupled to said control register means for providing one of said first or second address signals to said first alternately sequenced memory bank,

(B) selectively applying further address in said cache memory means from said address generator means and a fourth signal from said source of timing signals corresponding to a further address in said video generator means coupled to said control register means for providing one of said third or fourth address signals to said second alternately sequenced memory bank, and

(C) applying data stored in said first and second alternately sequenced memory banks in response to a control signal from said control register means and providing a data signal corresponding to a selected one of said sequenced memory banks to said video generator means in response to a control signal from said control register means,

wherein said control register means is operative to read in a first memory address command from said address generator means and store video processor data in a first one of said alternately sequenced memory banks while reading in a first memory address command from said source of timing signals to a second one of said alternately sequenced memory banks and reading out data stored therein to said video generator means and then reading in a second sequential memory address command from said source of timing signals to said first one of said alternately sequenced memory banks and reading out the data previously stored therein to said video generator means while reading in a second sequential memory address command from said address generator means and storing video processor data corresponding thereto into said second one of said alternately sequenced memory banks, so that said first and second alternately sequenced memory banks are caused to read in data and write out data in ping-pong fashion, one of said alternately sequenced memory banks being loaded with new video processor data while the other of said alternately said sequenced memory banks reads out its data into said video generator means.

57. The method as set forth in claim 56, further comprising the steps of alternately and sequentially storing map data in said first bank while map data stored in said second bank is read out for said display, and storing updated map data in said second bank while map data stored in said first bank is read out, and providing a pixel signal output corresponding to said map data, and

alternately and sequentially storing overlay data in second memory means having a said third bank while overlay data in a fourth bank thereof is read out for said display, and storing updated overlay data in said fourth bank while overlay data stored in said third bank thereof is read out, and switching means for

providing a pixel signal corresponding to said overlay data.

58. The method as set forth in claim 57 further comprising the steps of generating video data by:

converting a map data pixel signal to a first primary color signal in analog form and

converting an overlay data pixel signal to a second primary color signal in analog form.

59. The method as set forth in claim 58, further comprising the steps of generating video data by:

converting said map data pixel signal or said overlay data pixel signal to a monochrome signal in analog form, and

selectively outputting said first or second primary color signals or said monochrome signal.

60. The method as set forth in claim 59, further comprising the steps of generating video data by:

providing a first lookup table storage means for receiving at least a four bit digital word and providing an eight bit color word in digital form corresponding to a predetermined primary color value.

61. The method as set forth in claim 60, further comprising the steps of generating video data by:

providing a second lookup table storage means for receiving at least a four bit digital word and providing an eight bit word in digital form corresponding to a predetermined monochrome value.

62. The method as set forth in claim 61, further comprising the step of loading color values into at least two of said look-up table storage means simultaneously.

63. The method as set forth in claim 62, further comprising the step of providing a composite sync signal and combining said composite sync signal with a predetermined one of said signals in analog form.

64. The method as set forth in claim 63, further comprising the step of:

receiving optical signals in digital form and converting said optical signals to electrical signals in serial form,

converting said signals to parallel form and providing said converted signals to said cache memory means, and

initiating a block transfer of data from said memory unit controller means to said cache memory means.

65. The method as set forth in claim 64 further comprising the steps of:

providing x_i, y_j addresses to said first and second memory means for reading said pixel signals in sequential order corresponding to a predetermined frame rate and video resolution, and providing horizontal and vertical synchronizing signals, horizontal and vertical blanking signals, pixel clock and line video timing signals.

66. The method as set forth in claim 65 further comprising the steps of:

providing two interlaced fields of map or overlay data,

generating first starting addresses for said first field and second starting addresses for said second field,

generating sequential addresses along every other parallel line beginning with said first starting addresses to generate said first field of data and to generate sequential addresses along the parallel lines between said very other parallel line beginning with said second starting addresses to generate said second field of data interlaced with said first field of data,

synchronously with said vertical synchronization signal generating a ping-pong memory select signal for alternately and sequentially selecting one of said first or second memory banks and one of said third or fourth memory banks, for reading one of said first or second memory banks and writing into one other than said one of said first or second memory banks, and reading one of said third or forth memory banks and writing into one other than said one of said third or fourth memory banks.

67. The method as set forth in claim 66, further comprising the step of generating a ping-pong select signal synchronous with a predetermined video frame rate, wherein said video frame rate is comprised of three fields comprised of sequentially addressing said first and second fields of data.

68. The method as set forth in claim 67, said cache memory means further comprising:

providing a plurality of address selector switch means responsive to address signals, control signals, and map or overlay data, for selectively addressing one of a plurality of said storage segments,

selectively providing map and overlay data to be stored in said plurality of storage segments of said cache memory means, and

selectively enabling said first, second, or third buffer means for loading data from a first data bus coupled to said mass data controller means into said storage segments and for loading stored data into a second data bus coupled to said video processor means,

so that ones of said storage segments can be loaded with map or overlay data while still further ones of said storage segments can be simultaneously read into said first or second scene memories, whereby said scene memories can be loaded without contemporaneous access of said mass memory unit.

69. The method as set forth in claim 68 further comprising the step of storing an address in a display list register wherein associated overlay data is stored in at least one of said parallel planes.

70. The method as set forth in claim 69, further comprising the step of generating an analog video signal in RS-170A format.