Pseudo-Random code generator for use with a global positioning system
First Claim
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1. An apparatus for generating a pseudo-random code, comprising:
- a memory means for storing a set of pseudo-random codes, wherein the memory is allocated into a plurality of memory spaces each one word wide, with each bit in the word containing a bit for a different pseudo-random code, and wherein the length of the memory space is dependent on the length of the pseudo-random codes;
a first address means for selecting the memory space containing the desired pseudo-random code;
a counter operably coupled to a clock;
a second address means operably coupled to said counter to output a data word from the selected memory space of said memory with each clock cycle, where each word contains a bit associated with several possible pseudo-random codes;
a multiplexer operably coupled to said memory to select the bit associated with the selected pseudo-random code, whereby sequential bits for the selected pseudo-random code is generated with each clock cycle.
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Abstract
An apparatus for generating pseudo-random codes is disclosed. The apparatus uniquely stores a set of codes in a memory and uniquely retrieves a particular code sequence. The apparatus has particular application to Global Position Satellite (GPS) earth receivers.
23 Citations
1 Claim
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1. An apparatus for generating a pseudo-random code, comprising:
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a memory means for storing a set of pseudo-random codes, wherein the memory is allocated into a plurality of memory spaces each one word wide, with each bit in the word containing a bit for a different pseudo-random code, and wherein the length of the memory space is dependent on the length of the pseudo-random codes; a first address means for selecting the memory space containing the desired pseudo-random code; a counter operably coupled to a clock; a second address means operably coupled to said counter to output a data word from the selected memory space of said memory with each clock cycle, where each word contains a bit associated with several possible pseudo-random codes; a multiplexer operably coupled to said memory to select the bit associated with the selected pseudo-random code, whereby sequential bits for the selected pseudo-random code is generated with each clock cycle.
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Specification
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Current AssigneeJohns Hopkins University
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Original AssigneeJohns Hopkins University
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InventorsDevereux, William S., Westerfield, Edwin E.
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Primary Examiner(s)Malzahn, David H.
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Application NumberUS07/188,822Time in Patent Office540 DaysField of Search364/717, 331/78US Class Current708/250CPC Class CodesG01S 19/30 code related G01S19/246 tak...G06F 2207/581 Generating an LFSR sequence...G06F 7/584 using finite field arithmet...H03K 3/84 Generating pulses having a ...
