Failure information processing in automatic memory tester

• US 4,876,685 A
• Filed: 06/08/1987
• Issued: 10/24/1989
• Est. Priority Date: 06/08/1987
• Status: Expired due to Term

• Current Assignee: Teradyne Incorporated Boston MA
• Original Assignee: Teradyne Incorporated
• Inventors: Rich, Marc A.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Baker, Stephen M.
• Application Number:
  US07/059,550
• Time in Patent Office: 869 Days
• Field of Search: 324/73 R, 324/73 AT, 371/20, 371/21, 371/25, 371/10, 371/27, 371/24, 371/29
• US Class Current: 714/723
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response
• CPC Class Codes: G06F 11/32 with visual or acoustical indication of the functioning of the machine
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

Automatic memory tester apparatus for processing failure information of a memory under test (MUT) including a high speed pattern generator for providing digital test patterns to the MUT for storage of data at MUT addresses in the MUT, a failure processor for comparing outputs from the MUT with expected outputs to obtain failure information, and a fail map random access memory (RAM) having fail map addresses corresponding to the MUT addresses and connected to receive the failure information and store it at corresponding fail map addresses. The fail map addresses includes bits to address individual bits of multibit words. An address generator of the high speed pattern generator for randomly addresses and reads individual bits of the multibit words to provide a serial bit output for display. Relative positions of the display related to topical positions of associated memory elements on the MUT.

Claims

1. Automatic memory tester apparatus for processing failure information of a memory under test (MUT) having plural memory elements and associated MUT addresses, said apparatus comprising

a high speed pattern generator for providing digital test patterns to said MUT for storage of data at said MUT addresses in said MUT,

a failure processor for comparing outputs from said MUT with expected outputs to obtain failure information,

a fail map random access memory (RAM) having fail map addresses corresponding to said MUT addresses and connected to receive said failure information and store it at corresponding said fail map addresses, said fail map addresses including bits to address individual bits of multibit words,

address circuitry means for randomly addressing and reading individual bits of said multibit words to provide a serial bit output in which individual bits are in a different sequence than the sequence in which they are stored in said fail map RAM,

said different sequence relating to relative topical positions of said memory elements corresponding to individual bits of said serial bit sequences,

said address circuitry means including an address generator of said high-speed pattern generator connected to address said fail map RAM, and

means for receiving said serial bit output and visually displaying failure information in a two-dimensional display in which relative positions of display of said individual bits relate to topical positions of associated memory elements on said MUT.

2. The apparatus of claim 1 wherein said address circuitry comprises a descramble RAM for looking up addresses of bits of multibit words of said fail map RAM that correspond to addresses of bits of multibit words of said MUT.

3. The apparatus of claim 1 wherein said means for receiving and visually displaying comprises a computer connected to receive said serial output and a display to receive data from said computer and to visually display it.

4. The apparatus of claim 3 further comprising a shift register connected to receive and accumulate said serial output, and wherein said display is connected to receive serial output in accumulated form from said shift register.

5. The apparatus of claim 1 wherein said means for receiving and visually displaying comprises a computer connected to receive said serial output and a display to receive data from said computer and to visually display it.

6. The apparatus of claim 5 further comprising a flag register written to and read by said computer and said pattern generator.

7. The apparatus of claim 1 further comprising a data compressor to receive groups of bits of said serial bit output and to provide an error bit indicating if any bit of said group indicates an error.

8. The apparatus of claim 7 wherein said data compressor includes a first register that is connected to receive said serial bit output and a resettable feedback loop that maintains an overriding signal at the input of said first register upon detecting an error at the output of said register, said overriding signal being removed at the end of said group of bits, said data compressor including a second register that receives the output of the first register at the end of said group of bits.

9. The apparatus of claim 8 wherein said feed back loop includes an and gate having the output of said first register as one input and a SHIFT signal indicating the end of a group as another input, and said second register also receives said SHIFT signal.

10. The apparatus of claim 1 further comprising an and gate connected to receive said multibit stream and an IGNORE SERIAL ERROR signal causing it to ignore specified bits of said serial bit output.