Data demodulator

• US 4,876,700 A
• Filed: 04/16/1986
• Issued: 10/24/1989
• Est. Priority Date: 04/16/1986
• Status: Expired due to Term

• Current Assignee: Itron, Inc., E F Johnson Company (JVC Kenwood Corporation)
• Original Assignee: E F Johnson Company (JVC Kenwood Corporation)
• Inventors: Grindahl, Mervin L.
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/852,539
• Time in Patent Office: 1,287 Days
• Field of Search: 375/55, 375/84, 375/87, 375/95, 375/110, 375/13, 375/81, 375/82, 375/94, 375/120, 360/40, 360/43, 360/44, 360/51, 455/608, 329/50, 329/104
• US Class Current: 375/333
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A unique data recovery circuit which is able to recover transmitted digital data with a data clock embedded therein. No initial timing signals are required for operation of the data recovery circuit. Instead the data clock is recovered from the received data and used to synchronize the flow of data through the circuit. Noise pulses and other anomalous transients are rejected by the circuit so that the data output accurately corresponds to the data transmitted. Operation of the invention is achieved through a number of expedients which include a random access memory delay line which delays interpretation of the data until the data clock has been recovered. A uniquely integrated delay switching network is utilized to switch recovery of the clock from the received data to the delayed data. A phase locked loop and an integrate, sample and dump circuit are also employed, both of which use asynchronous ripple counters to achieve the primary objective of the invention which is to recover the data transmitted.

Claims

1. A data recovery circuit for demodulating transmitted encoded data comprising:

means for receiving the encoded data;

means for delaying the received encoded data for a delay time comprising a plurality of data bit time intervals;

means for recovering the transmitted data clock signal from either the received data during the delay time or from the delayed data after the delay time connected to the received data and to the delayed data;

means for switching the clock recovery means from the received data to the delayed data after a synchronization sequence of data bits has been received and for preventing switching from taking place until the logic level of the received data and the logic level of the delayed data are the same; and

means for decoding the delayed data with the recovered data clock signal.

2. A data recovery circuit for demodulating transmitted encoded data comprising:

means for receiving the encoded data;

means for delaying the received encoded data for a delay time comprising a plurality of data bit time intervals;

means for recovering the transmitted data clock signal from either the received data during the delay time or from the delayed data after the delay time;

means for switching the clock recovery means from the received data to the delayed data after a synchronization sequence of data bits has been received comprising an and/or select gate for selectively switching either the received data or the delayed data to the means for recovering the received data clock; and

means for decoding the delayed data with the recovered data clock signal.

3. A data recovery circuit for decoding transmitted data having a clock embedded therein comprising:

means for receiving the encoded data;

means connected to the receiving means and the master clock for synchronizing the received data with the master clock;

means connected to the receiving means for storing a plurality of bits of the received data;

means connected to the receiving means and the storage means for recovering the data clock signal embedded in the received data;

a phase locked loop connected to the clock recovery means for synchronizing the recovered data clock with the master clock;

a 90°

phase shift circuit connected to the phase locked loop for synchronizing the recovered clock with the delayed data;

a decoder means connected to the delayed data and to the recovered clock for decoding the data;

an integrate, sample and dump circuit connected to the delayed data to determine the logic level of the data; and

a delay switching circuit connected between the received data and the delayed data for switching the clock recovery circuit between the received data and the delay data after a predetermined sequence of synchronization bits have been received through the data recovery circuit.

4. A digital data recovery circuit for demodulating transmitted data comprising:

a master clock;

synchronization means operably connected to the master clock for receiving the transmitted data and synchronizing the received data with the master clock;

storage means operably connected to the synchronization means and the master clock for sampling and delaying the synchronized data;

a digital phase locked loop for recovering the data clock signal from the synchronized data comprising;

feedback means operably coupled to the master clock for generating a feedback pulse train having a frequency within a predetermined lock range;

comparison means operably coupled to the feedback means for receiving the synchronized data and the feedback pulse train and generating an output pulse train, the output pulse train having a duty cycle corresponding to the coincidence between the synchronized data and the feedback pulse train;

pulse inserter means operably connected to the feedback means and the master clock and the comparison means for generating a modified clock pulse train in response to the duty cycle of the output pulse train, whereby the modified lock pulse train is continuously modified to approach the frequency of the synchronized data when the frequency of the synchronized data is within the predetermined frequency lock range; and

phase shift means operably coupled to the comparison means for shifting the phase of the output pulse train to coincide with the phase of the synchronized data; and

decoder means operably connected to the digital phase locked loop and the storage means for decoding the delayed data with the recovered data clock signal.

5. The digital data recovery circuit of claim 4 wherein the synchronization means comprises an edge synchronization circuit.

6. A digital data demodulator circuit for receiving and demodulating encoded data transmitted as a data signal encoded with a data clock signal having a frequency within a specified range of frequencies, comprising:

a master clock having a frequency greater than the specified range;

synchronization means operably connected to the master clock for receiving the encoded data and synchronizing the encoded data with the master clock to produce a synchronized bit stream;

memory means operably connected to the synchronization means for storing the synchronized bit stream for a specified delay time to produce a delayed data bit stream;

clock recovery means operably connected to the synchronization means and the memory means for selectively recovering the data clock signal from the synchronized bit stream or from the delayed bit stream to produce a recovered clock signal;

data recovery means operably connected to the clock recovery means and the memory means for decoding the delayed bit stream to produce a recovered data signal; and

means operably connected to the data recovery means and the clock recovery means for receiving the recovered data signal and for switching the clock recovery means from the synchronized bit stream to the delayed bit stream after a synchronization series of data bits has been received.

7. The digital data demodulator circuit of claim 6 wherein the encoded data comprises Manchester encoded data.

8. The digital data demodulator circuit of claim 6 wherein the synchronization means comprises an edge synchronization circuit.

9. The digital data demodulator circuit of claim 6 wherein the memory means comprises a random access memory for storing a plurality of data bits and a ripple counter connected to the random access memory for sequentially storing the data bits in the memory.

10. The digital data demodulator circuit of claim 6 wherein the clock recovery means comprises a digital phase lock loop.

11. The digital data demodulator circuit of claim 10 wherein the digital phase lock loop comprises:

input means operably coupled to the synchronization means and the memory means for selectively providing an encoded pulse train of the synchronized bit stream or the delayed bit stream;

pulse inserter means operably coupled to the master clock for selectively inserting additional pulses into a master clock pulse train to generate a modified clock pulse train having a modified clock pulse train frequency;

feedback means operably coupled to the pulse inserter means for generating a feedback signal pulse train responsive to the modified clock pulse train frequency; and

comparator means operably coupled to the input means for providing a pulse inserter actuating signal in response to the comparative values of the encoded pulse train and the feedback signal pulse train, whereby the pulse inserter means is selectively actuated by the pulse inserter actuating signal to insert pulses into the master clock pulse train in response to the comparative values of the frequencies of the encoded pulse train and the feedback signal pulse train, and the feedback signal pulse train is thereby continuously modified to approach a predetermined value relative to the encoded pulse train.

12. The digital data demodulator circuit of claim 11 wherein the pulse inserter means comprises:

means operably coupled to the master clock for changing the phase of the master clock pulse train;

means operably coupled to the comparator means and the master clock for triggering the change in phase of the master clock pulse train in response to the pulse inserter actuating signal; and

means operably coupled to the means for changing the phase and the means for triggering the change in phase for delaying the change in phase of the master clock pulse train long enough to generate an additional pulse in the modified clock pulse train.

13. The digital data demodulator circuit of claim 11 wherein the feedback means comprises an asynchronous ripple counter.

14. The digital data demodulator circuit of claim 11 wherein the comparator means comprises a phase detector.

15. The digital data demodulator circuit of claim 11 wherein the predetermined value relative to the input signal is a square wave having a frequency equal to, but ninety degrees out of phase with the encoded pulse train and wherein said digital data demodulator circuit further comprises phase shift means operably coupled to said feedback means for shifting the phase of the feedback pulse train signal ninety degrees, thereby producing the recovered clock signal in phase with the encoded pulse train.

16. The digital data demodulator circuit of claim 6 wherein the data recovery means comprises:

a decoder operably connected to the memory means and the clock recovery means; and

an integrate, sample and dump circuit operably connected to the decoder.

17. A digital data demodulator circuit for receiving and demodulating Manchester encoded data transmitted as a data signal encoded with a data clock signal having a frequency within a specified range of frequencies, comprising:

a master clock having a frequency substantially greater than the specified range;

edge synchronization means operably connected to the master clock for receiving the encoded data and edgesynchronizing the encoded data with the master clock to produce a synchronized encoded data bit stream;

memory means operably connected to the synchronization means for storing the encoded data bit stream for a specified delay time to produce a delayed encoded data bit stream, comprising;

random access memory for storing a plurality of data bits; and

a ripple counter connected to the random access memory for sequentially storing the data bits in the random access memory;

a digital phase lock loop operably connected to the synchronization means and the memory means for selectively recovering the data clock signal from the synchronized encoded data bit stream or from the delayed encoded data bit stream to produce a recovered clock signal;

data recovery means operably connected to the clock recovery means and the memory means for decoding the delayed encoded data bit stream to produce a recovered data signal, comprising;

a decoder operably connected to the memory means and the clock recovery means; and

an integrate, sample and dump circuit operably connected to the decoder; and

means operably connected the data recovery means and the clock recovery means for receiving the recovered data signal and for switching the clock recovery means from recovering the synchronized encoded data bit stream to recovering the delayed encoded data bit stream after a synchronization series of data bits has been received,

whereby the data signal and the data clock signal are recovered from the same sequence of transmitted Manchester encoded data without the need for a precursor sequence consisting of only timing information.

18. A data recovery circuit for demodulating Manchester encoded data transmitted at a specified data clock frequency and having an identification field followed by a data field, comprising:

a master clock having a frequency greater than the specified frequency;

edge synchronization means operably connected to the master clock for receiving the encoded data and synchronizing the edge of the encoded data with the edge of the master clock to produce a synchronized encoded data signal;

sampling means operably connected to the edge synchronization means and the master clock for sampling the synchronized encoded data signal at the master clock frequency to produce a sampled bit stream with each encoded data bit of the Manchester encoded data represented as a plurality of sampled bits;

memory means operably connected to the sampling means for delaying the sampled bit stream a delay time comprising a plurality of encoded data bit time intervals to produce a delayed bit stream;

clock recovery means operably connected to the sampling means and the memory means for recovering the data clock signal from the sampled bit stream or the delayed bit stream;

data recovery means operably connected to the clock recovery means and the memory means for decoding the delayed bit stream with the recovered data clock signal to produce a sequence of decoded data bits; and

means operably connected to the data recovery means and the clock recovery means for determining whether to recover the data clock signal from the sampled bit stream or from the delayed bit stream, comprising;

means for receiving the decoded data bits operably connected to the data recovery means;

means for examining the decoded data bits for a series of synchronization data bits in the identification field operably connected to the means for receiving; and

means for switching the clock recovery means from recovering the data clock signal from the sampled bit stream to recovering the data clock signal from the delayed bit stream after the series of synchronization data bits are received operably connected to the means for examining and the clock recovery means,

whereby the data clock signal is recovered from the sampled bit stream during the delay time and during the examination of the decoded data bits for the series of synchronization data bits in the identification field and then the clock recovery means is switched and the data clock signal is recovered from the delayed bit stream for decoding the data field.

19. A method for demodulating encoded data transmitted as a data signal encoded with a data clock signal having a frequency within a specified range of frequencies, comprising the steps of:

receiving the encoded data;

synchronizing the received data with a master clock having a frequency greater than the specified range;

delaying the synchronized data for a delay time comprising a plurality of data bit time intervals;

recovering the data clock signal from the undelayed data;

decoding the delayed data with the recovered undelayed data clock signal;

examining the decoded data for a series of synchronization data bits;

switching to recovering the data clock signal from the delayed data after receiving the series of synchronization data bit; and

decoding the remaining delayed data with the recovered delayed data clock signal.

20. A method for demodulating Manchester encoded data transmitted at a specified data clock frequency and having an identification field followed by a data field, comprising the steps of:

receiving the Manchester encoded data;

synchronizing the edge of the received data with the edge of a master clock having a frequency greater than the specified data clock frequency;

sampling the synchronized data at the master clock frequency to produce a sample bit stream with each encoded data bit of the Manchester encoded data represented as a plurality of sampled bits;

delaying the sampled bit stream for a delay time comprising a plurality of encoded data bit time intervals;

recovering the data clock signal from the undelayed bit stream;

decoding the delayed data with the recovered undelayed data clock signal;

examining the decoded data for a series of synchronization data bits in the identification field;

recovering the data clock signal from the delayed bit stream after the series of synchronization data bits are received; and

decoding the remaining delayed bit stream comprising the data field with the recovered delayed data clock signal.