Image sensor array for still camera imaging with multiplexer for separating interlaced fields

• US 4,878,121 A
• Filed: 07/09/1987
• Issued: 10/31/1989
• Est. Priority Date: 07/09/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hynecek, Jaroslva
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Bauer, Robert M.
• Application Number:
  US07/071,447
• Time in Patent Office: 845 Days
• Field of Search: 358/213.23, 358/213.25, 358/213.26, 358/909, 358/44, 358/213.22
• US Class Current: 348/319
• CPC Class Codes: H04N 25/713 Transfer or readout registers; Split readout registers or multiple readout registers
• CPC Class Codes: H04N 25/715 using frame interline transfer [FIT]
• CPC Class Codes: H04N 25/72 using frame transfer [FT]

Abstract

A CCD imager (10) is adaptable for recording a still image and translating the still image into a NTSC television format. An image array (12) of the imager (10) has a plurality of cells arranged in rows and columns (35-37). The cells are further divided into a plurality of fields including a first field and a second field, cells in any one row belong to a single field. A memory array (16) of the imager comprises a plurality of memory cells (128, 130, 82, 84, 174, 176, 152 and 154) including first cells (128, 82, 174, 152) for storing signals from the first field, and second cells (130, 84, 176, 54) for storing signals from the second field. A transferor (14) is operable to transfer the first field signals to the first memory cells (128, 174, 152), and also transfers the second field signals to the second memory cells (130, 84, 176, 154). A readout circuit (18-32) reads out the first field signals from the first memory cells (128, 82, 174, 152) during a first period, and reads out the second field signals from the second memory cells (130, 84, 176, 154) during a second period following the first period.

Claims

1. An imager formed at a face of a semiconductor substrate for recording a still image and for translating the still image into a selected television format, comprising:

a frame transfer image array having a plurality of image cells, said image cells accumulating charge in response to input light and arranged in a plurality of rows and columns, odd numbered ones of said rows constituting a first field and even numbered ones of said rows constituting a second field;

a memory array having a first plurality of memory cells including first cells arranged in first memory columns for storing first field signals contained in said first field and second cells arranged in second memory columns for storing second field signals contained in said second field;

a multiplexer coupled between the image array and the memory array for enabling transfer of groups of n charges in said first field signals to said first memory cells and like groups of n charges in said second field signals to said second memory cells;

wherein n is greater than 2 and

a readout circuit for reading out said first and said second field signals from said first and second memory cells.

2. The imager of claim 1, wherein said multiplexer comprises a plurality of column sections each coupled to a corresponding image array column section, said multiplexer column sections each comprising a plurality of columns equal to said plurality of columns in each said image array column section;

a first column of each said multiplexer column section receiving a signal from a first column in a corresponding image array column section, a second column of said multiplexer column section receiving a signal from a second column of said corresponding image array column section;

said multiplexer disposed between said image array and said memory array, gate means in said multiplexer for advancing the signal in said first multiplexer column toward said memory array ahead of the signal in said second multiplexer column;

a gate for transferring the signal in said second multiplexer column to a location in said first multiplexer column behind said first signal with respect to said memory array; and

a gate disposed at an end of each said first multiplexer column for sequentially transferring said signals to a selected memory column.

3. The memory array of claim 2, wherein said columns in each multiplexer column section each comprise a plurality of serially connected CCD cells for transferring charges from said image array columns through said CCD cells to said selected memory column;

each CCD cell in said multiplexer having at least one well formed in said semiconductor substrate, at least one selected well of each said first multiplexer column having a greater length in the direction of said memory array than a corresponding well in said second multiplexer column, such that said selected well is displaced toward said memory array relative to said corresponding well.

4. The imager of claim 2, wherein said first and second columns of said multiplexer column section each comprise a plurality of CCD cells, each CCD cell having at least one well and one barrier formed in said semiconductor substrate, a junction well in said first multiplexer column disposed adjacent a first barrier, said first barrier disposed adjacent a well of an upstream CCD cell in said first multiplexer column, a second barrier disposed adjacent said junction well, said second barrier disposed adjacent a selected well in said second multiplexer column, said selected well in said second column operable to transfer signals to said junction well to thereby transfer signals from said second multiplexer column to said first multiplexer column.

5. The imager array of claim 4, wherein each said multiplexer column section comprises said first and second multiplexer columns and a third multiplexer column, said third column comprising a plurality of CCD cells each having at least one well, the CCD cells in each multiplexer column disposed in a line between said image array and said memory array, each multiplexer column operable to receive a signal from a respective last CCD cell in said image array;

said wells in said second multiplexer column including a junction well, a last well in said third multiplexer column disposed farthest from said image array of the wells in said third multiplexer column, said last well disposed adjacent a vertical barrier separating said last well in said third column from said junction well in said second column;

a last well of said wells in said second column disposed farthest from said image array of the wells in said second multiplexer column, said last well in said second column disposed adjacent a vertical barrier, said vertical barrier disposed adjacent said junction well in said first column, such that each said multiplexer column section is operable to transfer signals from each column in row of a respective image array column section into a selected column of a respective column section in said memory array.

6. The imager of claim 4, wherein each said CCD cell inside said multiplexer is a virtual phase CCD cell having a clocked well and a virtual well, said last well of said third multiplexer column and said last well of said second multiplexer column each comprising a clocked well, said junction well of said second multiplexer column and said junction well of said first multiplexer column each comprising a virtual well.

7. The imager of claim 1, wherein said memory array comprises a plurality of memory column sections each having a first and a second memory column, said first memory columns operable to store signals from said fist field, said second memory columns operable to store signals from said second field;

said readout means operable to select either said first memory columns or said second memory columns for reading out said signals from either said first field or said second field.

8. The imager of claim 7, wherein said transferor comprises a multiplexer having a plurality of multiplexer sections, said image array divided into image column sections each having a plurality of image columns each multiplexer section coupled to each image column in a respective image column section for receiving said first and second field signals;

a memory column section provided for each multiplexer column section, each said multiplexer column section having an output well for transferring said first and second field signals to either the first or the second memory column of a respective memory array column section.

9. The imager of claim 8, wherein said first and second memory columns each comprise a plurality of CCD wells formed at a face of a semiconductor substrate, each first memory column includes a first clocked well, said first clocked well disposed adjacent a first barrier, said first barrier disposed adjacent an output well of a respective multiplexer section;

each second memory column including a second clocked well, said second clocked well disposed adjacent a second barrier, said second barrier disposed adjacent said output well of said respective multiplexer section;

said first clocked well and said second clocked well clocked by alternating phase clocks such that a signal stored in said output well is operable to be transferred into either said first clocked well or said second clocked well.

10. The imager of claim 1, wherein said image array comprises an interline transfer image array, said interline transfer image array comprising a plurality of sensor cells arranged in columns, each column of sensor cells formed adjacent a channel formed in parallel to said column, said first and second cells of said memory array disposed in respective first and second memory columns, an output of each said image array channel selectively coupled by said multiplexer to at least two columns of said memory array;

signals accumulated in each column of said sensor cells operable to be transferred into a respective channel, said channel operable to transfer signals serially down said channel to said multiplexer, said transferor operable to transfer each said signal from said channel to a selected column in said memory array.

11. The imager of claim 10, wherein said multiplexer comprises:

an input for each pair of columns in said memory array, an output for each image array channel, a first input of a first memory column and a second input of a second memory column coupled to said output of a respective image array channel, said first input clocked by a first clock source, said second input clocked by a second clock source alternating with said first clock source, signals in said channel operable to be transferred into a selected one of said first and second memory column inputs responsive to an active state of a corresponding clock source.

12. The imager of claim 1, wherein said first cells of said memory array are disposed in first channels at a face of a semiconductor layer, said second cells of said memory array disposed in second channels in said face and insulatively disposed in parallel to said first channels;

first channels are disposed in first channel pairs insulatively adjacent each other, second channels are insulatively disposed adjacent each other in second channel pairs, said first and second channel pairs alternating across said memory array, each cell in each channel paired with a cell in a paired channel in a direction orthogonal to said channels.

13. The imager of claim 12, wherein said first and second memory cells comprise virtual phase CCD cells, each said virtual phase CCD cell having a clocked well and a virtual well, each clocked well of a first cell in one channel paired with a clocked well of a first cell in a paired channel, each clocked well of a second cell in one channel paired with a clock well of a second cell in a paired channel;

said paired clocked wells of said first cells having a single integral first gate conductor insulatively disposed thereover, said paired clocked wells of said second cells having a single integral second gate conductor insulatively disposed thereover, first conductive means for coupling each first gate conductor to a first clock source, second conductive means for coupling each second gate conductor to a second clock source, such that the transmission of signals into and through said first and second wells may be controlled independently of each other.

14. The imager of claim 13, wherein said first conductive means comprises a plurality of conductive links insulatively disposed above said first channel pairs to join together all first gate conductors disposed over each first channel pair, selected ones of first gate conductors connected to a first phase clock conductor;

said second conductor means comprising a plurality of conductive links insulatively disposed above said second channel pairs, selected ones of said second gate conductors connected to a second phase clock conductor.

15. The imager of claim 14, wherein said clocked wells of said CCD memory cells are disposed in rows orthogonal to said channels in said memory array;

odd rows of said clocked well rows each having a first phase clock conductor insulatively disposed thereover, even rows of said clocked well rows each having a second phase clock conductor insulatively disposed thereover, an even row spaced between each proximate pair of odd rows;

a conductive contact made within between each first phase clock conductor and each first gate conductor in a respective odd row, a conductive contact made between each second phase clock conductor and each second gate conductor in a respective even row.

16. Apparatus for sensing, storing and transmitting a still image formed at a face of a semiconductor substrate, comprising:

a frame transfer image array having a plurality of image cells formed at said face and arranged in parallel rows and channels orthogonal to said rows, each image cell operable to accumulate a charge responsive to incident light;

said frame transfer image array divided into a plurality of channel sections, each channel section having a plurality of channels, the image cells in each channel coupled in series;

each channel terminating in a terminal cell, a multiplexer formed at said face and disposed adjacent said terminal cells, said multiplexer having a receiver for receiving charges from each terminal cell in said respective channel section in parallel and a transmitter for transmitting said charges in series;

a memory array having a plurality of memory cells arranged in rows and in a plurality of channels orthogonal to said rows, said channels forming channel pairs, each pair having a first channel and a second channel, input cells of said first and second channels in each channel pair coupled to the transmitter of a respective multiplexer section;

each said transmitter operable to transfer charges from said output cell serially to either a first or a second memory channel input cell in a respective memory channel pair; and

a serial register for reading out charges from either said first channel in parallel or said second channel in parallel into a register section, said register section operable to be serially read out.

17. The apparatus of claim 16, wherein said serial register further contains a plurality of register cells disposed in said face, each memory channel pair having first and second end cells disposed remotely from channel input cells, a plurality of gates of said serial register each disposed adjacent a respective first and a respective second end cell for transmitting a charge from either a first end cell or a second end cell into a register cell.

18. The apparatus of claim 17, and further comprising:

a plurality of serial registers, a first serial register coupled to said end cells in said memory array by said gates, a plurality of first transfer gates selectively coupling respective cells of said first serial register to respective cells of a second serial register, a plurality of second transfer gates selectively coupling respective cells of said second serial register with respective cells of a third serial register, a plurality of third transfer gates selectively coupling respective cells of said third serial register with a drain region;

said serial registers each operable to transmit charges encoding information for a respective one of three colors as sensed by said image array, said transfer gates operable to selectively transfer charges to the correct serial register and to selectively dump said charges to said drain.

19. The apparatus of claim 16, wherein odd rows of said frame transfer image array comprise a first field of image pixels, even rows of said frame transfer image array comprising a second field of image pixels;

charges from said odd rows operable to be transferred by said multiplexer to said first channels of said memory array, charges from even rows of said frame transfer image array operable to be transferred by said multiplexer to said second channels of said memory array;

said serial register operable to read out charges from said first channels and then to read out charges from said second channels.

20. The apparatus of claim 16, wherein said multiplexer comprises a plurality of multiplexer sections each having a plurality of input cells, each input cell coupled to a terminal cell of a respective channel section, said input cells operable to receive respective charges from said terminal cells in parallel, an output cell of each multiplexer section operable to serially transmit charges received by said input cells.

21. A method for and transferring a visual image, comprising:

sensing an image with an image sensor array having a plurality of image cells, said cells comprising a first field of cells and a second field of cells;

transferring the first field of cells to odd columns of memory cells in a single memory array;

accumulating a first field of charges responsive to light incident on odd rows of the cells in the image array;

accumulating a second field of charges responsive to light incident on even rows of the cells in the image array;

transferring the second field of cells to second even columns of memory cells in the single memory array; and

reading out the charge accumulated in the memory cells in the single memory array.

22. The method of claim 21 and further including the steps of:

storing charges of any predetermined charge group from cells in the image array that were laterally vertically adjacent each other, so as to be laterally adjacent to each other in the memory array;

merging the charge in each cell in each odd column with the charge stored in a laterally adjacent cell in the adjacent even column in said memory array; and

reading out the merged odd and even charges in a video movie mode.

23. The method of claim 21 wherein said step of transferring charges from the rows of the image array to said memory array includes the steps of:

dividing the image array into a plurality of channel sections each comprising a like plurality of image array channels;

transferring the charges accumulated in the image array into a multiplexer one row at a time, the step of transferring including the substeps of;

transferring a charge group in a channel section into a corresponding multiplexer section, each charge group comprising a plurality of charges orignating from a single row within a channel section;

in each multiplexer section, arranging the charges of the charge group in a serial order;

for each multiplexer section, serially outputting the arranged charge group from a single multiplexer section output;

for each multiplexer section, transferring the charge group to either a respective first column in the memory array or a respective second column in the memory array, depending on whether the charge group comes from an odd image array row or an even image array row;

performing said steps of transferring to the multiplexer section, arranging the charge groups in serial fashion and transferring the charge groups to the memory array until all of the charges in the image array have been transferred to the memory array;

serially reading out the charges in the odd columns of the memory array; and

serially reading out the charges in the even columns of the memory array.

24. The method of claim 23, wherein each charge group comprises three charges respectively accumulated responsive to a different color of light, the method comprising the further steps of:

for each pair of first and second columns in the memory array;

repeating said steps of transfering arranging, outputting and transferring within the memory array until all charges from the image array have been stored, the first and second rows charge groups to be stored then occupying the last three cells in each column of the memory array;

clocking a charge pixel of a charge group stored in the first column of the memory array into a cell of a first serial register;

simultaneously clocking the first charge through a first transfer gate into a cell of a second serial register and clocking a second charge of the charge group into the cell of the first said serial register;

simultaneously clocking the first charge through a second transfer gate into a cell of a third register, the second charge through the first transfer gate into the cell of the second register, and the third charge of the charge group into the cell of the first serial register;

serially transferring out the charge groups present in the serial register;

repeating the above steps for the remaining charge groups in the odd memory columns; and

repeating all of the above steps for the charge groups stored in the even memory columns.

25. A method for recording, storing and reading out a still image, comprising the steps of:

accumulating a plurality of charges due to incident light, the charges organized into charge groups, a plurality of charge groups formed in respective image cells in a row in an imager array, the imager array having a plurality of rows and columns of image cells;

transferring the charge groups from the image array to a memory array through a multiplexer, having a plurality of multiplexer sections, said step of transferring including the substeps of;

moving the charge groups in each row of image cells into an adjacent row toward the multiplexer;

simultaneously transferring the charge groups in a last row of image cells adjacent to the multiplexer into the multiplexer, each charge group being transferred into a corresponding multiplexer section;

within each multiplexer section, arranging each charge group in a predetermined sequential order;

if the charge group within an associated multiplier section originated in an odd row of the image array, serially outputting the charge group in the sequential order from the multiplexer to a first group of cells of a first odd column in the memory array, the number of cells equal to the number of charges in the charge group;

if the image array row from which the charge group originated was an even row, serially outputting the charge group to a first group of cells of a first even column of the memory array.

transferring the current contents of the first group of cells in the first odd column or the first even column to a next number of cells in the first odd or first even column depending upon which column the charge group was serially output;

repeating the above steps until all charge groups have been transferred into the memory array;

reading out the charges stored in the first odd columns; and

reading out the charges stored in the even columns.

26. The method of claim 25, wherein said steps of reading out the pixel groups from the odd and even columns in the memory array include the substeps of:

providing a plurality of serial registers equal in number to the number of charges in each charge group, cells of a first serial register coupled to a last row of cells in the memory array, transfer gates disposed between corresponding cells of the serial registers to provide pathways for transferring each charge into a requisite serial register;

clocking a first charge group in each odd column a number of times equal to the number of charges in the group to transfer each charge in the pixel group to a cell in a corresponding serial register;

serially transferring out the first charge groups to outputs of the serial registers;

moving a next charge group in each odd column to the end of the column nearest the serial registers;

transferring a next charge group in each odd column into the serial registers;

repeating said step of transferring charge groups into the serial register and reading out the charge groups from the serial register until charge groups in each of the odd columns have been read out; and

repeating the above steps of transferring the charge groups into the serial register and reading out the charge groups from the serial registers for the even columns in the memory array.