Direct memory access apparatus and methods for transferring data between buses having different performance characteristics
First Claim
1. Direct memory access means having a plurality of operating states each indicated by a status signal for transferring data to and from a first bus to which a first set of devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of devices, having performance characteristics differing from said first set of devices, is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices without adversely affecting the performance of said first set of devices and said second set of devices, comprising:
- (a) access means, operating independent of CPU intervention, coupled to said first bus and to said second bus, including at least one direct memory access channel means for determining data transfer addresses, wherein said direct memory access channel means has said plurality of operating states each of which is indicated by a status signal, and further wherein said access means is utilized for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus;
(b) means for interconnecting said first bus to said access means;
(c) means for interconnecting said second bus to said access means; and
(d) a set of internal registers included within said access means, coupled to and receiving inputs from said first bus, wherein said set of internal registers are accessed by said direct memory access channel means for determining said data transfer addresses, where the contents of the set of internal registers are used for controlling and maintaining a given direct memory access channel operating state and the status indication associated therewith.
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Abstract
Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the transfer function in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. Direct memory access ("DMA") apparatus and methods are disclosed, including a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DMA interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. The noval DMA may also be used as part of a data transfer controller (DTC) having other components, such as I/O ports, or may be used independently for transferring data between unmatched buses in, for example, computer systems, data transmission systems and the like.
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Citations
44 Claims
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1. Direct memory access means having a plurality of operating states each indicated by a status signal for transferring data to and from a first bus to which a first set of devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of devices, having performance characteristics differing from said first set of devices, is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices without adversely affecting the performance of said first set of devices and said second set of devices, comprising:
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(a) access means, operating independent of CPU intervention, coupled to said first bus and to said second bus, including at least one direct memory access channel means for determining data transfer addresses, wherein said direct memory access channel means has said plurality of operating states each of which is indicated by a status signal, and further wherein said access means is utilized for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus; (b) means for interconnecting said first bus to said access means; (c) means for interconnecting said second bus to said access means; and (d) a set of internal registers included within said access means, coupled to and receiving inputs from said first bus, wherein said set of internal registers are accessed by said direct memory access channel means for determining said data transfer addresses, where the contents of the set of internal registers are used for controlling and maintaining a given direct memory access channel operating state and the status indication associated therewith. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method for transferring data to and from a first bus, to which a first set of devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of devices, having performance characteristics differing from said first set of devices, is attached, comprising the steps of:
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(a) transferring data between said first bus and said second bus, at a variable transfer rate, utilizing direct memory access means, for performing a CPU independent data transfer, wherein said direct memory access means includes at least one direct memory access channel means, coupled to said buses for determining data transfer addresses, wherein said direct memory access channel means has a plurality of operating states each of which is indicated by a status signal, and further wherein said direct memory access means is utilized for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus; (b) decoupling, via said direct memory access channel means, the latency and bandwidth of accesses on said first bus from the latency and bandwidth of accesses on said second bus, with concurrency between accesses on both buses, so that the performance of said first set of devices and said second set of devices each having differing performance characteristics are not adversely affected when transferring data between said first and second bus via said direct memory access means; and (c) initializing a set of registers included within said direct memory access means, coupled to said first bus, wherein said set of registers are accessed by said direct memory access channel means for determining said data transfer addresses, where the contents of said set of registers are used for controlling said direct memory access means. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44)
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Specification