Direct memory access apparatus and methods for transferring data between buses having different performance characteristics

• US 4,878,166 A
• Filed: 12/15/1987
• Issued: 10/31/1989
• Est. Priority Date: 12/15/1987
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dutton, Drew J., Olson, Timothy A., Lee, Sherman, Johnson, William M., Stoenner, David W.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/133,094
• Time in Patent Office: 686 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/307
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the transfer function in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. Direct memory access ("DMA") apparatus and methods are disclosed, including a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DMA interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. The noval DMA may also be used as part of a data transfer controller (DTC) having other components, such as I/O ports, or may be used independently for transferring data between unmatched buses in, for example, computer systems, data transmission systems and the like.

Claims

1. Direct memory access means having a plurality of operating states each indicated by a status signal for transferring data to and from a first bus to which a first set of devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of devices, having performance characteristics differing from said first set of devices, is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices without adversely affecting the performance of said first set of devices and said second set of devices, comprising:

(a) access means, operating independent of CPU intervention, coupled to said first bus and to said second bus, including at least one direct memory access channel means for determining data transfer addresses, wherein said direct memory access channel means has said plurality of operating states each of which is indicated by a status signal, and further wherein said access means is utilized for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus;

(b) means for interconnecting said first bus to said access means;

(c) means for interconnecting said second bus to said access means; and

(d) a set of internal registers included within said access means, coupled to and receiving inputs from said first bus, wherein said set of internal registers are accessed by said direct memory access channel means for determining said data transfer addresses, where the contents of the set of internal registers are used for controlling and maintaining a given direct memory access channel operating state and the status indication associated therewith.

2. Direct memory access means as set forth in claim 1 wherein said means for interconnecting said second bus to said access means further comprises packing and funneling network means, coupled to said access means, for accommodating variable width data transfers between said first bus and said second bus.

3. Direct memory access means as set forth in claim 2 further comprising means coupled to said second bus, for prioritizing access to said channel means whenever a plurality of direct memory access channel means exists.

4. Direct memory access means as set forth in claim 2 wherein said access means further, comprises:

(a) queue means, coupled to both said first and second buses for buffering data being transferred between said first bus and said second bus; and

(b) programmable internal register means for controlling the operation of said queue means.

5. Direct memory access means as set forth in claim 4 wherein each of said direct memory access channel means further comprises:

(a) first multiplexing means for selectively transferring word length data input to said access means from said first bus and for selectively transferring packed data, input to said access means from said packing and funneling network means, into said queue means;

(b) first packing/funneling register means, coupled to said first mutiplexing means and said packing and funneling network means, for storing data during packing and funneling operations;

(c) second multiplexing means for selectively transferring data output from said queue means, to be funneled to said packing and funneling network means via said first packing/funneling register means, and for selectively transferring packed data input from said packing and funneling network to said first multiplexing means via said first packing/funneling register means.

6. Direct memory access means as set forth in claim 4 wherein the data buffered in said queue means may be directly manipulated by said CPU to avoid latency associated with data transfers between said first bus and said queue means.

7. Direct memory access means as set forth in claim 4 further comprising means, coupled to said second bus and said queue means, for performing bus sizing.

8. Direct memory access means as set forth in claim 2 wherein said packing and funneling network means further comprises:

(a) means for packing data on a transfer from said second bus to said first bus, including means for converting a number of byte and half word transfers on said second bus to a smaller number of half words and word transfers on said first bus; and

(b) means for buffering data being packed, by said means for packing data, in order to facilitate full word transfers of packed data to said first bus.

9. Direct memory access means as set forth in claim 2 wherein said packing and funneling network means further comprises:

(a) means for funneling data on a transfer from said first bus to said second bus, including means for converting a number of word and half word transfers on said first bus to a larger number of half word and byte transfers on said second bus; and

(b) means for buffering data being funneled, by said means for funneling, in order to enable said means for funneling to extract half words and bytes of buffered data one at a time for transfer to said second bus.

10. Direct memory access means as set forth in claim 1 wherein said means for interconnecting said first bus to said access means further comprises means for initializing said set of internal registers.

11. Direct memory access means as set forth in claim 10 further comprising a plurality of signal paths used for carrying signals between said CPU and said set of internal registers, in order to initialize and control data transfer operations.

12. Direct memory access means as set forth in claim 11 wherein said plurality of signal paths comprise the pins of an integrated circuit package.

13. Direct memory access means as set forth in claim 1 wherein said access means is programmable.

14. Direct memory access means as set forth in claim 13 wherein said access means is programmed during initialization by said CPU to determine data transfer addresses independent of said CPU during transfer operations.

15. Direct memory access means as set forth in claim 1 further comprising means for decoupling the operation of said access means from program execution by said CPU to thereby permit said CPU and said access means to operate concurrently.

16. Direct memory access means as set forth in claim 1 wherein said access means further comprises means for performing nonsequential transfers independent of CPU intervention.

17. Direct memory access means as set forth in claim 1 wherein said access means further comprises transfer rate control means for controlling the rate of data transfer between said first bus and said second bus.

18. Direct memory access means as set forth in claim 1 operative to permit direct memory access channel means operation to overlap with the operation of said set of devices attached to said first bus.

19. Direct memory access means as set forth in claim 1 further comprising means, coupled to both said first and second buses, for performing data packing and unpacking.

20. Direct memory access means as set forth in claim 1 further comprising means, coupled to both said first and second buses, for swapping data packet location in words being transferred.

21. Direct memory access means as set forth in claim 1 wherein said access means further comprises means for decoupling the latency and bandwidth of accesses on said first bus from the latency and bandwidth of accesses on said second bus, with concurrency between accesses on both buses.

22. Direct memory access means as set forth in claim 1 wherein said access means may be configured to support block and pattern transfers between said first and second buses.

23. Direct memory access means as set forth in claim 1 suitable for transferring data between two synchronous buses.

24. Direct memory access means as set forth in claim 1 suitable for transferring data between two asynchronous buses.

25. Direct memory access means as set forth in claim 1 having a test mode of operation.

26. Direct memory access means as set forth in claim 1 operable in parallel with at least one data transfer controller, to which it is connected, in a master/slave relationship.

27. A method for transferring data to and from a first bus, to which a first set of devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of devices, having performance characteristics differing from said first set of devices, is attached, comprising the steps of:

(a) transferring data between said first bus and said second bus, at a variable transfer rate, utilizing direct memory access means, for performing a CPU independent data transfer, wherein said direct memory access means includes at least one direct memory access channel means, coupled to said buses for determining data transfer addresses, wherein said direct memory access channel means has a plurality of operating states each of which is indicated by a status signal, and further wherein said direct memory access means is utilized for channelling direct memory access transfers from said first bus to said second bus and from said second bus to said first bus;

(b) decoupling, via said direct memory access channel means, the latency and bandwidth of accesses on said first bus from the latency and bandwidth of accesses on said second bus, with concurrency between accesses on both buses, so that the performance of said first set of devices and said second set of devices each having differing performance characteristics are not adversely affected when transferring data between said first and second bus via said direct memory access means; and

(c) initializing a set of registers included within said direct memory access means, coupled to said first bus, wherein said set of registers are accessed by said direct memory access channel means for determining said data transfer addresses, where the contents of said set of registers are used for controlling said direct memory access means.

28. A method as set forth in claim 27 wherein said step of transferring further comprises the step of packing data being transferred from said second bus to said first bus to accommodate variable width data transfers.

29. A method as set forth in claim 28 wherein said step of transferring further comprises the step of funneling data being transferred from said first bus to said second bus to accommodate variable width data transfers.

30. A method as set forth in claim 29 wherein said step of transferring further comprises the step of multiplexing address signals and data signals being transferred to said second bus by said direct memory access means.

31. A method as set forth in claim 29 wherein said step of decoupling via said direct memory access channel means further comprises the step of storing data being transferred between said first bus and said second bus, into a storage means, having a queue organization, used for buffering data, under the control of programmed register means used for controlling said buffering.

32. A method as set forth in claim 31 wherein the step of decoupling via said direct memory access channel means further comprises the step of multiplexing word length data input to said direct memory access means from said first bus with packed word length data being transferred via said direct memory access means from said second bus, for buffering in said storage means.

33. A method as set forth in claim 31 wherein the data buffered in said storage means may be directly manipulated by said CPU to avoid the latency associated with data transfers between said first bus and said storage means.

34. A method as set forth in claim 27 wherein the step of transferring further comprises the step of funneling data on a transfer from said first bus to said second bus wherein said step of funneling further includes the step of converting a number of word and half word transfers on said first bus to a larger number of half word and byte transfers on said second bus.

35. A method as set forth in claim 34 wherein said step of converting further comprises the steps of:

(a) buffering data being funneled; and

(b) extracting half words and bytes of buffered data, one at a time, for transfer to said second bus.

36. A method as set forth in claim 27 wherein said step of transferring further comprises the step of prioritizing access to said direct memory access channel means whenever a plurality of channel means exists.

37. A method as set forth in claim 27 wherein said step of transferring further comprises the step of checking parity for both data and address transfers.

38. A method as set forth in claim 27 wherein said step of decoupling when transferring via said direct memory access means is accomplished by decoupling the operation of said direct memory access means from program execution by said CPU.

39. A method as set forth in claim 27 wherein said step of decoupling via said direct memory access channel means further comprises the step of initializing, via said CPU during initialization, said direct memory access means to determine data transfer addresses independent of the CPU operation.

40. A method as set forth in claim 27 wherein said step of transferring via said direct memory access means is performed nonsequentially.

41. A method as set forth in claim 27 wherein the step of decoupling via said direct memory access channel means further comprises the step of controlling said variable transfer rate between said first bus and said second bus.

42. A method as set forth in claim 27 wherein the step of transferring further comprises the step of performing bus sizing.

43. A method as set forth in claim 27 wherein said step of decoupling via said direct memory access channel means further comprises the step of overlapping direct memory access channel means operation with the operation of said set of devices attached to said first bus.

44. A method as set forth in claim 27 wherein the step of transferring further comprises the steps of:

(a) packing data on a transfer from said second bus wherein said step of packing further includes the step of converting a number of byte and half word transfers on said second bus to a smaller number of half words and word transfers on said first bus; and

(b) buffering data being packed in order to facilitate full word transfers of packed data to said first bus.