Floating point/integer processor with divide and square root functions

• US 4,878,190 A
• Filed: 01/29/1988
• Issued: 10/31/1989
• Est. Priority Date: 01/29/1988
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Wang, Paul C., Earl, Dale C., Dodrill, Jim, Ngo, Dinh T., Hipona, Maria B. L., Gill, Michael C., Darley, Henry M.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Mai, Tan V.
• Application Number:
  US07/150,363
• Time in Patent Office: 641 Days
• Field of Search: 364/761, 364/764, 364/766-767, 364/752, 364/715.03, 364/754, 364/757, 364/745
• US Class Current: 708/605
• CPC Class Codes: G06F 2207/5355 Using iterative approximation not using digit recurrence, e.g. Newton Raphson or Goldschmidt
• CPC Class Codes: G06F 7/4824 using signed-digit representation
• CPC Class Codes: G06F 7/4873 Dividing
• CPC Class Codes: G06F 7/49957 Implementation of IEEE-754 Standard
• CPC Class Codes: G06F 7/535 Dividing only
• CPC Class Codes: G06F 7/5525 Roots or inverse roots of single operands

Abstract

A processor (10) operable to calculate division and square root functions comprises a multiplier (48) having a multiplier array (116), a pipeline register (50), a correction generator (122), and a converter/rounder (52). The products generated by the multiplier array (116) are fed back to the multiplier (48) to avoid delays associated with the remainder of the multiplier circuitry. The correction generator (122) which performs a subtraction of the product output form the multiplier array (116) from a constant, is disposed between the multiplier array (116) and the converter/rounder (52). Hence, the subtraction necessry to compute the next estimate may be performed in parallel with other multiplications, further reducing the time necessary to perform the calculation. Compare circuitry (120) is operable to compare the final approximation with an operand to quickly determine the direction of rounding.

Claims

1. Apparatus for calculating a selected value of a quotient or a square root of an operand, comprising:

multiplier circuitry having at least first and second inputs receiving first and second numeric signals respectively, said multiplier circuitry including a first portion for producing a product of the first and second numeric signals representing an approximation of the value and a second portion for producing a conversion of said product into a predetermined numeric representation;

first feedback circuitry transmitting said conversion to the first input of the multiplier circuitry; and

second feedback circuitry transmitting said product to the second input of said multiplier circuitry.

2. The apparatus of claim 1 wherein said multiplier circuitry further includes a subtracter connected between said first portion and said second portion for subtracting said product from a constant value.

3. The apparatus of claim 1 wherein said multiplier circuitry further includes a pipeline register connected between said first portion and said subtracter.

4. The apparatus of claim 1 wherein said first portion includes circuitry to produce a signed digit product.

5. The apparatus of claim 1 wherein said second numeric signal can be a signed digit number or a binary number.

6. The apparatus of claim 1 wherein said second feedback circuitry includes a first memory coupled between said first portion and said first input of said multiplier circuitry.

7. The apparatus of claim 1 wherein said second feedback circuitry further includes:

a first multiplexer coupled between the first memory and a second memory; and

a second multiplexer coupled between the second memory and the second input to the multiplier circuitry.

8. The apparatus of claim 1 wherein the selected value is the quotient and further includes a seed generator coupled to the first and second inputs of said multiplier circuitry for generating an approximation of the reciprocal of a divisor of the operand.

9. The apparatus of claim 8 wherein the second multiplexer receives signals from the second memory, the seed generator, a first register storing the operand, and a state control circuit and transmits as output said second numeric signal.

10. The apparatus of claim 8 wherein a third multiplexer receives signals from the seed generator, the second portion of the multiplier circuitry, a second register storing the divisor and the state control circuit.

11. The apparatus of claim 8 wherein said second portion further includes rounding and compare circuitry coupled between said second portion and said second feedback circuitry for comparing a product of the quotient and the divisor with the operand for determining a direction for rounding the quotient.

12. The apparatus of claim 1 wherein the selected value is the square root and further includes a seed generator coupled to the first and second inputs of said multiplier circuitry for generating an approximation of a reciprocal of the square root of the operand.

13. The apparatus of claim 1 wherein said second portion further includes rounding and compare circuitry coupled between said second portion and said second feedback circuitry for comparing a square of the square root with the operand for determining a direction for rounding the square root.

14. The apparatus of claim 1 wherein said predetermined numeric representation is a binary magnitude representation.