Integrated trench-transistor structure and fabrication process

• US 4,881,105 A
• Filed: 06/13/1988
• Issued: 11/14/1989
• Est. Priority Date: 06/13/1988
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hwang, Wei, Davari, Bijan, Lu, Nicky C.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Jackson, Jr. Jerome
• Application Number:
  US07/206,148
• Time in Patent Office: 519 Days
• Field of Search: 357/23.4, 357/55, 357/42, 357/49, 357/54, 357/46, 437/203, 437/72
• US Class Current: 257/334
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0925 comprising an N-well only in the substrate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer is grown on a substrate and contains an n-well, an n+ source and a p+ source regions. Shallow trenches are disposed in the epitaxial layer and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region connects the trenches and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer of silicon dioxide on the trench walls of the gates. The p+ drain region, along with the filled trench gate element and the p+ source region, form a vertical p-channel (PMOS) trench-transistor. The n+ drain region, along with filled trench gate element and the n+ source form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions and an oxide layer.

Claims

1. An integrated, self-aligned trench-transistor structure comprising:

a substrate of semiconductor material,

a layer of epitaxial material,

a well region disposed in said epitaxial layer,

a first source element region disposed in said well region,

a second source element region disposed in said epitaxial layer proximate to said well region,

a first trench disposed in said epitaxial layer and into said first source element in said well region, said first trench being filled with conductive material to form a first gate element region,

a second trench disposed in said epitaxial layer and into said second source element region, said second trench being filled with conductive material to form a second gate element region,

a first drain element region disposed in the surface of said epitaxial layer around said first filled trench,

a second drain element region disposed in the surface of said epitaxial layer around said second filled trench,

said first filled trench gate element region, said first source element region and said first drain element region forming a first conductivity type vertical transistor,

said second filled trench gate element region, said second source element region and said second drain element region forming a second conductivity type vertical transistor,

a region of conductive material connecting said conductive gate material in said first trench and said conductive gate material in said second trench,

a third trench disposed in said epitaxial layer and into said first source element region in said well region proximate to said first trench, said third trench being filled with conductive material to form a third gate element region, and

a third drain element region disposed in the surface of said epitaxial layer around said third trench,

said third trench gate element region, said first source element region and said third drain element region forming a first conductivity type vertical trench strapping transistor for providing bias signal to said first source element region.

2. An integrated, self-aligned trench transistor structure according to claim 1 further including a fourth trench disposed in said epitaxial layer and into said second source element region, proximate to said trench, said fourth trench being filled with conductive material to form a fourth gate element region,

a fourth drain element region disposed in the surface of said epitaxial layer around said fourth trench, and

said fourth filled trench gate element region said second source element region ad said fourth drain element region forming a second conductivity type vertical trench strapping transistor for providing a bias signal to said second source element.

3. An integrated, self-aligned trench-transistor structure according to claim 2 wherein said epitaxial layer is composed of p-type material, said well region is composed of n- material, said first source element region is composed of p+ material, and

said first drain element region is composed of p+ material to form in combination with said first trench gate element a vertical p-channel first PMOS trench-transistor and

wherein said second source element region is composed of n+ material, and

said second drain element region is composed of n+ material to form in combination with said second trench gate element a vertical n-channel first NMOS trench-transistor.

4. An integrated, self-aligned trench-transistor structure according to claim 3 further including a layer of oxide isolation material disposed over said epitaxial layer, said oxide layer having openings located over said first and second trenches wherein said openings in said oxide layer are filled with conductive material in contact with said conductive material in said first and second trenches, and

wherein said conductive material disposed in said openings in said oxide layer are isolated from said oxide layer by vertical nitride spacer regions disposed in said openings.

5. An integrated, self-aligned trench-transistor structure according to claim 4 wherein said first and second trenches include a layer of isolation material on the walls thereof, and wherein a region of isolation material is disposed in the surface of said epitaxial layer intermediate said PMOS and NMOS vertical trench-transistors.

6. An integrated, self-aligned trench-transistor structure according to claim 3 wherein said third drain element region is composed of p+ material to form in combination with said first p+ material source element region and said third trench gate element region a vertical second PMOS strapping transistor.

7. An integrated, self-aligned trench-transistor structure according to claim 6 wherein said fourth drain element region is composed of n+ material to form in combination with said second n+ material source element region and said fourth trench gate element region a vertical second NMOS strapping transistor.

8. An integrated, self-aligned trench-transistor structure according to claim 7 further including a layer of oxide isolation material disposed over said epitaxial layer, said oxide layer having openings located over said first, second, third and fourth trenches wherein said openings in said oxide layer are filled with conductive material in contact with said conductive material in said first, second, third and fourth trenches, and

wherein said conductive material disposed in said openings in said oxide layer are isolated from said oxide layer by vertical nitride spacer regions disposed in said openings.

9. An integrated, self-aligned trench-transistor structure according to claim 7 wherein said third and fourth trenches include a layer of isolation material on the walls thereof, and

wherein regions of isolation material are disposed on the surface of said epitaxial material between said first and third trenches and said second and fourth trenches.

10. An integrated, self-aligned trench-transistor structure according to claim 9 further including

said first source element in said epitaxial layer having drain and gate elements similar to said first PMOS vertical transistor,

a third NMOS vertical transistor deposited in said second source element in said epitaxial layer having drain and gate elements similar to said first NMOS vertical transistor,

means for connecting a voltage source to said gate elements of said second PMOS vertical strapping transistor and said second NMOS vertical strapping transistor,

means for connecting a voltage source to said third drain element of said second PMOS vertical strapping transistor,

means for connecting a reference potential to said fourth drain element of said second NMOS strapping transistor,

an input signal terminal connected to said first and second gate elements of said first PMOS and first NMOS vertical trench-transistors, and

an output signal terminal connected to said drain elements of said third PMOS and third NMOS vertical transistors to provide a CMOS inverter structure.

11. An integrated, self-aligned trench-transistor structure according to claim 9 further including

a third source element disposed proximate to said first source element in said n-well region in said epitaxial layer,

a fourth source element disposed in said epitaxial layer proximate to said second source element,

a third PMOS vertical transistor disposed in said first source element in said epitaxial layer having drain and gate elements similar to said first PMOS vertical transistor,

a third NMOS vertical transistor disposed in said second source element in said epitaxial layer having drain and gate elements similar to said first NMOS vertical transistor,

fourth and fifth PMOS vertical transistors disposed in said third source element and having drain and gate elements similar to said first, second and third PMOS vertical transistors,

fourth and fifth NMOS vertical transistors disposed in said fourth source element and having drain and gate elements similar to said first, second and third NMOS vertical transistors,

means for connecting a voltage source to said third drain element of said second PMOS strapping transistor and to said third gate element of said second NMOS strapping transistor,

means for connecting a reference source to said third gate element of said second PMOS strapping transistor and to said third drain element of said second NMOS strapping transistor,

means for connecting said gate elements of said first NMOS and fourth PMOS vertical transistors together to a first input terminal,

means for connecting said gate elements of said third NMOS and fifth PMOS vertical transistors together to a second input terminal,

means for connecting said gate element of said fourth NMOS and first PMOS vertical transistor together to a third input terminal,

means for connecting said gate elements of said third PMOS vertical transistor, said drain element of said fifth PMOS vertical transistor, said gate element of said fifth NMOS and said drain element of said third NMOS transistor together, and

means for connecting said drain elements of said first PMOS, third PMOS and fifth NMOS vertical trench-transistors to an output terminal to provide a vertical CMOS NOR/NAND gate structure.