Process for forming an epitaxial layer having portions of different thicknesses

• US 4,882,294 A
• Filed: 08/17/1988
• Issued: 11/21/1989
• Est. Priority Date: 08/17/1988
• Status: Expired due to Term

• Current Assignee: Delphi Technologies, Inc. (BorgWarner Incorporated)
• Original Assignee: Delco Electronics Corporation (Motors Liquidation Co. GUC Trust)
• Inventors: Christenson, John C.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): EVERHART, BYRON S
• Application Number:
  US07/233,319
• Time in Patent Office: 461 Days
• Field of Search: 437/77, 437/83, 437/84, 437/89, 437/90, 437/93, 437/99, 437/126, 437/970, 148/DIG. 29, 148/DIG. 150, 148/DIG. 152
• US Class Current: 438/340
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/8222 Bipolar technology
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS

Abstract

An integrated circuit device uses a silicon chip having an epitaxial layer which has two portions of different thicknesses in which are formed separate junction transistors of different characteristics. In the growth of the epitaxial layer there is first formed on the front surface of the chip a localized sacrificial silicon dioxide layer removable in situ by baking in a reducing atmosphere. Then an epitaxial layer is grown by a first epitaxial deposition phase selectively over only the silicon dioxide free regions of the front surface of the chip. The sacrificial silicon dioxide layer is then removed in situ by baking in hydrogen. There is then resumed blanket growth of the epitaxial layer by a second epitaxial deposition phase. In the resulting chip, a large geometry junction transistor of relatively low switching speed and moderately high breakdown voltage (compared to 12 volts) is formed in the thicker epitaxial portion and a small geometry junction transistor of high switching speed and lower breakdown voltage is formed in the thinner epitaxial portion.

Claims

1. In the manufacture of an integrated circuit in a semiconductive wafer, the process of forming in the wafer an epitaxial layer having portions of at least two different thicknesses comprising the steps of:

preparing one surface of a monocrystalline semiconductive wafer for the growth thereon of epitaxial material;

forming over at least one region of said one surface of the wafer a sacrificial masking layer of a material that can serve as a barrier to the nucleation of epitaxial material thereover and that can be removed in situ, while leaving at least one other region of said one surface of the wafer free of the sacrificial masking layer;

heating the wafer in a furnace in which there is an ambient suitable for depositing the desired epitaxial material to a first thickness selectively over regions of the one surface free of the sacrificial masking layer;

treating the one surface of the wafer in situ in an ambient suitable for removing selectively the sacrificial masking layer at least at the other regions of the one surface for exposing the underlying regions of the one surface; and

heating the wafer in an ambient suitable for the deposition of epitaxial material both over the previously deposited epitaxial material and over the exposed regions of the one surface, thereby to form an epitaxial layer over said one surface having portions of different thickness.

2. The process of claim 1 in which the semiconductive wafer is silicon and the sacrificial masking layer is a silicon oxide that is removable by baking in a reducing ambient.

3. The process of claim 2 in which the sacrificial masking layer is of essentially uniform thickness and is entirely removed by said baking in a hydrogen ambient.

4. The process of claim 2 in which:

the sacrificial masking layer is initially formed of two regions of different thicknesses and the thinner of the two regions is removed in a first removal step following the deposition of the desired epitaxial material to a first thickness;

the thicker of the two regions is removed in a second removal step after the previously deposited epitaxial material has had its thickness increased to the second thickness in a second deposition step; and

then the wafer is heated again in an ambient suitable for the blanket deposition of additional epitaxial material over the wafer as a third deposition step, whereby there is formed over the wafer an epitaxial layer having portions of three different thicknesses.

19. The process of claim 1 in which the one surface of the monocrystalline semiconductive wafer is initially non-planar because the wafer has at least one thinner portion, and the portion of the epitaxial layer of greater thickness is deposited in the thinner portion of the wafer, whereby the deposited epitaxial layer deposited restores substantial planarity to said one surface.

20. The process of claim 1 in which the one surface of the monocrystalline silicon wafer initially includes a mesa portion and the thicker portion of the two portions of the epitaxial layer is deposited selectively over the top surface of the mesa portion whereby the effective height of the mesa is increased after deposition of the epitaxial layer.

5. A process for forming an epitaxial layer having portions of two different thicknesses on a silicon monocrystalline wafer comprising the steps of:

forming over one surface portion of the wafer a sacrificial layer of a silicon oxide;

patterning the sacrificial layer thereby to expose selected regions of said surface portion of the wafer;

heating the wafer in a suitable ambient for growing epitaxial silicon to form an epitaxial layer portion of a first thickness selectively localized at said exposed selected regions;

removing in situ the patterned sacrificial layer by baking the wafer in a hydrogen atmosphere for a sufficient period of time, thereby exposing the remainder of said one surface portion of the wafer; and

reheating the wafer in a suitable ambient for growing epitaxial silicon to thicken said epitaxial layer portion of first thickness to a larger thickness and to form over said remainder of said one surface portion of the wafer an epitaxial layer portion of thickness smaller than said first thickness.

6. The process of claim 5 in which the patterned sacrificial layer has a thickness of at least 5 Angstroms.

7. The process of claim 6 in which said first thickness is about three microns, said larger thickness is about five microns, and said smaller thickness is about two microns.

8. The process of claim 5 in which the heating and reheating steps and the baking step are all performed in the same furnace without removal of the wafer from the furnace until said heating, reheating and baking steps have been completed.

9. The process of claim 5 in which the ambient for said heating step is a gaseous mixture comprising dichlorosilane and hydrochloric acid.

10. The process of claim 9 in which the ambient for said reheating step is a gaseous mixture comprising silicon tetrachloride.

11. The process of claim 10 in which the sacrificial layer is of silicon oxide reducible in a hydrogen ambient.

12. The process of claim 11 in which the sacrificial silicon oxide layer has a thickness of at least 75 Angstroms.

13. The process of claim 12 in which the sacrificial silicon oxide layer has a thickness of between 75 and 150 Angstroms.

14. The process of claim 13 in which the first thickness is about three microns, the larger thickness is about five microns and the smaller thickness is about two microns.

15. The process of claim 5 in which at least one transistor is formed in each of the portions of the epitaxial layer of different thicknesses.

16. The process of claim 15 in which the transistor formed in the thicker epitaxial portion is designed to tolerate higher voltages than the transistor formed in the thinner epitaxial portion but the latter transistor has a higher switching speed than the former transistor.

17. A process for forming over a surface portion of a semiconductor wafer an epitaxial layer having three portions of different thickness comprising:

forming on said one surface of the wafer a sacrificial masking layer having regions of two different thicknesses, and including apertures exposing regions of the one surface portion of the wafer;

depositing epitaxial material selectively only on the exposed regions of the one surface portion of the wafer;

removing in situ the thinner of the two regions of different thicknesses of the sacrificial masking layer for exposing further regions of the one surface portion of the wafer;

depositing epitaxial material selectively only on the exposed regions of the one surface portion of the wafer;

removing in situ the remainder of the sacrificial masking layer for exposing the remainder of the one surface portion of the wafer; and

depositing expitaxial material in blanket fashion over said one surface portion of the wafer.

18. A process for forming an epitaxial layer having portions of at least three different thicknesses over a surface portion of a wafer comprising the steps of:

forming over said surface portion a sacrificial masking layer having at least two portions of different removal characteristics and including apertures for exposing regions of the surface portion of the wafer;

depositing epitaxial material selectively only on the exposed regions of said surface portion of the wafer;

removing in situ selectively one of the two portions of the sacrificial masking layer for exposing further regions of said surface portion of the wafer;

depositing epitaxial material selectively only on the exposed regions of said surface portion of the wafer;

removing in situ selectively the other portion of the two portions of the sacrificial masking layer to expose further regions of said surface portion of the wafer; and

depositing epitaxial material over the exposed regions of said surface portions of the wafer.

21. A process for forming over a moncrystalline substrate an epitaxial layer having portions of n different thickness comprising the steps of:

forming over a surface of the substrate a sacrificial masking layer made up of at least n-1 portions, each of which is selectively removable;

placing the substrate in a furnace and growing epitaxial material selectively over unmasked portions of the surface of the substrate;

removing selectively one portion of the sacrificial masking layer without withdrawing the substrate from the furnace;

growing epitaxial material selectively over unmasked surface portions of the substrate; and

repeating in turn said removing selectively step and growing epitaxial material selectively step without withdrawing the substrate from the furnace until portions of n different thicknesses of epitaxial material have been grown over the surface of the substrate.

22. The process of claim 21 in which the sacrificial masking layer formed on the surface of the substrate has n-1 portions of different thicknesses.

23. The process of claim 21 in which the sacrificial masking layer formed on the surface of the substrate has n-1 portions different in either thickness or in composition.