Synchronous semiconductor memory device

• US 4,882,712 A
• Filed: 09/26/1988
• Issued: 11/21/1989
• Est. Priority Date: 09/29/1987
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited, Fujitsu VLSI Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited, Fujitsu VLSI Limited (Fujitsu Limited)
• Inventors: Ohno, Chikai, Hirata, Michiyuki
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/249,058
• Time in Patent Office: 421 Days
• Field of Search: 365/206, 365/189.01, 365/189.05, 365/230.01
• US Class Current: 365/206
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A synchronous semiconductor memory device has a noise preventing part for preventing a noise from being transmitted to a memory cell array, where the noise is caused by a change in a write data.

Claims

1. A synchronous semiconductor memory device comprising:

first latch means for latching a write command in synchronism with a clock signal;

second latch means for latching a write data in synchronism with the clock signal and for outputting two write process signals based on the write data latched thereby;

pulse generating means for generating an internal write pulse signal based on the write command latched by said first latch means, said internal write pulse signal having a first logic level only in a write mode of the synchronous semiconductor memory device;

write control means supplied with said internal write pulse signal and said write process signals for controlling write and read operations of the synchronous semiconductor memory device;

memory means for storing the write data latched by said second latch means; and

noise preventing means coupled to said second latch means and said write control means for supplying said write process signals to said write control means only in the write mode responsive to said internal write pulse signal and for setting said write process signals to fixed potentials during a time other than the write mode.

2. A synchronous semiconductor memory device as claimed in claim 1 in which said write control means supplies the write data latched by said second latch means to said memory means in the write mode and cuts off the supply of the write data to said memory means in a read mode of the synchronous semiconductor memory device so as to apply a constant read potential to said memory means.

3. A synchronous semiconductor memory device as claimed in claim 1 in which said first and second latch means respectively latch the write command and the write data at a transition of the clock signal from the first logic level to a second logic level, hold the write command and the write data during a time when the clock signal has the first logic level, and pass the write command and the write data as they are during a time when the clock signal has the second logic level.

4. A synchronous semiconductor memory device as claimed in claim 1 in which said pulse generating means includes a clock gate circuit supplied with the clock signal and the write command latched by said first latch means for outputting a start signal which is a logical sum of the write command and an inverted signal of the clock signal, and a write pulse generating circuit for outputting said internal write pulse signal based on the clock signal responsive to the start signal from said clock gate circuit.

5. A synchronous semiconductor memory device as claimed in claim 1 in which said noise preventing means has a clamp circuit for clamping the write process signals to a second logic level during a time when said internal write pulse signal has the second logic level and for cancelling the clamping of the write process signals during a time when said internal write pulse signal has the first logic level.

6. A synchronous semiconductor memory device as claimed in claim 1 in which said write command has a first transition from a second logic level to the first logic level a set up time before a transition of the clock signal from the first logic level to the second logic level and a second transition from the first logic level to the second logic level after a hold time from said transition of the clock signal and at least the set up time before a next transition of the clock signal from the first logic level to the second logic level, said set up time and said hold time being set up and hold times of said first latch means.

7. A synchronous semiconductor memory device as claimed in claim 6 in which said internal write pulse signal has the first logic level only for a predetermined time, said predetermined time being a sum of said set up time and said hold time.

8. A synchronous semiconductor memory device as claimed in claim 1 in which said internal write pulse signal has the first logic level only for a predetermined time.

9. A synchronous semiconductor memory device as claimed in claim 1 in which said noise preventing means transmits the write data latched by said second latch means to said write control means as the write process signals in the write mode when the internal write pulse signal has the first logic level and clamps the write process signals to a second logic value in a read mode when the internal write pulse signal has the second logic level.