Method and apparatus for addressing a cache memory
DCFirst Claim
1. A microprocessor comprising:
- a first addressable memory forming a data cache;
a second addressable memory forming an instruction cache, the instruction cache being separate from the data cache;
execution means for processing data received from the data cache in response to an instruction from the instruction cache;
data interface means, coupled to the data cache and to the execution means, for independently controlling access to the data cache and for communicating data from the data cache to the execution means; and
instruction interface means, coupled to the instruction cache and to the execution means, for independently controlling access to the instruction cache and for communicating instructions from the instruction cache to the execution means, the instruction interface means including;
a counter for addressing the instruction cache;
instruction address loading means, coupled to the counter, for storing a first address in the counter; and
cache advance means for repetitively generating a non-address cache advance signal for incrementing the counter after the first address is stored in the counter, the counter being incremented once per cache advance signal, and the cache advance means operating independently of the instruction address loading means.
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Abstract
A microprocessor architecture is disclosed having separate very high speed instruction and data interface circuitry for coupling via respective separate very high speed instruction and data interface buses to respective external instruction cache and data cache circuitry. The microprocessor is comprised of an instruction interface, a data interface, and an execution unit. The instruction interface controls communications with the external instruction cache and couples the instructions from the instruction cache to the microprocessor at very high speed. The data interface controls communications with the external data cache and communicates data bidirectionally at very high speed between the data cache and the microprocessor. The execution unit selectively processes the data received via the data interface from the data cache responsive to the execution unit decoding and executing a respective one of the instructions received via the instruction interface from the instruction cache. In one embodiment, the external instruction cache is comprised of a program counter and addressable memory for outputting stored instructions responsive to its program counter and to an instruction cache advance signal output from the instruction interface. Circuitry in the instruction interface selectively outputs an initial instruction address for storage in the instruction cache program counter responsive to a context switch or branch, such that the instruction interface repetitively couples a plurality of instructions from the instruction cache to the microprocessor responsive to the cache advance signal, independent of and without the need for any intermediate or further address output from the instruction interface to the instruction cache except upon the occurrence of another context switch or branch.
125 Citations
16 Claims
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1. A microprocessor comprising:
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a first addressable memory forming a data cache; a second addressable memory forming an instruction cache, the instruction cache being separate from the data cache; execution means for processing data received from the data cache in response to an instruction from the instruction cache; data interface means, coupled to the data cache and to the execution means, for independently controlling access to the data cache and for communicating data from the data cache to the execution means; and instruction interface means, coupled to the instruction cache and to the execution means, for independently controlling access to the instruction cache and for communicating instructions from the instruction cache to the execution means, the instruction interface means including; a counter for addressing the instruction cache; instruction address loading means, coupled to the counter, for storing a first address in the counter; and cache advance means for repetitively generating a non-address cache advance signal for incrementing the counter after the first address is stored in the counter, the counter being incremented once per cache advance signal, and the cache advance means operating independently of the instruction address loading means. - View Dependent Claims (2, 3, 16)
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4. A method for communicating instructions between an instruction cache and a processor comprising the steps of:
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(a) storing a first address value in a counter; (b) addressing the instruction cache with the value stored in the counter; (c) communicating an instruction stored in the addressed location of the instruction cache to a multistage instruction buffer; (d) serially communicating the instructions stored in the instruction buffer to the processor; (e) generating a cache advance signal when a stage in the instruction buffer is empty; (f) independently incrementing the counter in response to the cache advance signal; and (g) repeating steps (b) through (f) until the occurrence of either one of a context switch or a branch. - View Dependent Claims (5)
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6. A microprocessor comprising:
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an addressable cache memory; execution means for processing digital information received from the cache memory; and interface means, coupled to the cache memory and to the execution means, for retrieving digital information from the cache memory and for communicating the retrieved digital information to the execution means, the interface means comprising; a counter coupled to the memory, a value stored in the counter being used for addressing the cache memory; address loading means, coupled to the counter and to the execution means, for storing an address from the execution means in the counter; and incrementing means, coupled to the counter, for selectively incrementing the address stored in the counter; wherein the address loading means operates independently of the incrementing means. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification