Address generator with variable scan patterns
First Claim
1. An address generator for scanning a first addressable memory logically configures in a rectangular matrix wherein a pattern of data is stored in a predetermined orientation with respect to said matrix, and for writing to a second addressable memory comprising:
- input means for receiving parameters from an external source, said parameters being programmable for providing a predetermined scan pattern from a plurality of scan patterns substantially independent of said predetermined orientation,processor means coupled to receive said parameters for computing angles of an envelope defining the contour of a scan pattern and angles of rotation for successive lines of said scan pattern.read address generator means responsive to said processor means for selectively generating address signals so as to read out said pattern information in a given direction with respect to said predetermined orientation, wherein said given direction is substantially independent of said predetermined orientation, and for providing incremental horizontal and vertical values of read addresses for generating each line of said scan pattern and reading values of digital signals stored in said first memory at corresponding addresses,write address generator means coupled to receive said parameters in the form of a first parameter defining a starting point of a first scan line, a second parameter defining the slope of said scan line, and a third parameter defining the slope of starting points of successive scan line, said first, second, and third parameters being dynamically and sequentially variable in accordance with command signals from said external source to form one of said plurality of scan patterns, for generating sequential write addresses for writing into said second addressable memory configured in a rectangular matrix,counter means for counting the number of incremental addresses in accordance with a predetermined line length and the number of scan lines in accordance with a predetermined line count and for providing a signal indicative of the completion of a scan line and a signal indicative of the generation of a complete frame at the completion of said line count, andtiming means for generating timing and sequencing signals for generating each scan line, reading said first addressable memory along said scan lines, and writing the contents of said addressable memory into said second addressable memory.
1 Assignment
0 Petitions
Accused Products
Abstract
An apparatus for reading a first addressable memory and writing into a second addressable memory wherein the first addressable memory is logically arranged in a rectangular matrix and is scanned at an arbitrary angle with respect to the matrix for producing a plurality of scan patterns whose parameters can be altered and controlled by an external source, while the second addressable memory, also arranged in a rectangular matrix, is written into along parallel rows and columns. The apparatus is particularly adapted for use with a digital map display system having an airborne computer for generation the scan parameters.
23 Citations
14 Claims
-
1. An address generator for scanning a first addressable memory logically configures in a rectangular matrix wherein a pattern of data is stored in a predetermined orientation with respect to said matrix, and for writing to a second addressable memory comprising:
-
input means for receiving parameters from an external source, said parameters being programmable for providing a predetermined scan pattern from a plurality of scan patterns substantially independent of said predetermined orientation, processor means coupled to receive said parameters for computing angles of an envelope defining the contour of a scan pattern and angles of rotation for successive lines of said scan pattern. read address generator means responsive to said processor means for selectively generating address signals so as to read out said pattern information in a given direction with respect to said predetermined orientation, wherein said given direction is substantially independent of said predetermined orientation, and for providing incremental horizontal and vertical values of read addresses for generating each line of said scan pattern and reading values of digital signals stored in said first memory at corresponding addresses, write address generator means coupled to receive said parameters in the form of a first parameter defining a starting point of a first scan line, a second parameter defining the slope of said scan line, and a third parameter defining the slope of starting points of successive scan line, said first, second, and third parameters being dynamically and sequentially variable in accordance with command signals from said external source to form one of said plurality of scan patterns, for generating sequential write addresses for writing into said second addressable memory configured in a rectangular matrix, counter means for counting the number of incremental addresses in accordance with a predetermined line length and the number of scan lines in accordance with a predetermined line count and for providing a signal indicative of the completion of a scan line and a signal indicative of the generation of a complete frame at the completion of said line count, and timing means for generating timing and sequencing signals for generating each scan line, reading said first addressable memory along said scan lines, and writing the contents of said addressable memory into said second addressable memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. An address generator for scanning a first addressable memory logically configures in a rectangular matrix and writing to a second addressable memory comprising:
-
input means for receiving parameters from an external source, said parameters being programmable for providing a predetermined scan pattern, processor means coupled to receive said parameters for computing angles of an envelope defining the contour of a scan pattern and angles of rotation for successive lines of said scan pattern, read address generator means responsive to said processor means for providing incremental horizontal and vertical values of read addresses for generating each line of said scan pattern and reading values of digital signals stored in said first memory at corresponding addresses, write address generator means coupled to receive said scan pattern for generating sequential write addresses for writing into said second addressable memory configures in a rectangular matrix, counter means for counting the number of incremental addresses in accordance with a predetermined line length and the number of scan lines in accordance with a predetermined line count and for providing a signal indicative of the completion of a scan line and a signal indicative of the generation of a completed frame at the completion of said line count, and timing means for generating timing and sequencing signals for generating each scan line, reading said first addressable memory along said scan lines, and writing the con tents of said first addressable memory into said second addressable memory; wherein said read address generator means comprises; an X read address generator and a Y read address generator for receiving parameters representative of the starting address of a scan line, first incremental X and Y correction values corresponding to a slope of said scan line, and second incremental X and Y correction values corresponding to the relative slope of successive scan lines, means for computing read addresses corresponding to at least one of said scan lines by summing the respective X and Y starting addresses and corresponding first X and Y incremental values and sequentially incrementing said summed read addresses by said first incremental values, means responsive to the completion of a scan line for summing the respective X and Y starting points and corresponding second X and Y incremental values, thereby defining the start of a successive scan line, and means for sequentially incrementing said read address by summing said first and second X and Y incremental values therewith until a predetermined plurality of scan lines defining a frame is completed. - View Dependent Claims (10, 11, 12, 13)
-
-
14. A method for scanning a first addressable memory logically configured in a rectangular matrix and writing to a second addressable memory comprising:
-
providing control parameters from an external source, said parameters being programmable for providing a predetermined scan pattern, applying said parameters to a processor and computing angles of an envelope defining the contour of a scan pattern and angles of rotation for successive lines of said scan pattern, deriving incremental horizontal and vertical read address values for generating each line of said scan pattern from said computed angles, and reading values of digital signals stored in said first addressable memory at corresponding addresses, generating sequential write addresses for writing into said second addressable memory configured in a rectangular matrix, counting the number of incremental addresses in accordance with a predetermined line length and the number of scan lines in accordance with a predetermined line count and providing a signal indicative of the completion of a scan line and a signal indicative of the generation of a complete frame at the completion of said line count, generating timing and sequencing signals for generating each scan line, reading said first addressable memory along said scan lines and writing the contents of said first addressable memory into said second addressable memory, applying said parameters representative of the starting address of a scan line, first incremental X and Y correction values corresponding to a slope of said scan line, and second incremental X and Y correction values corresponding to the relative slope of successive scan lines to corresponding X and Y read address generators, computing read addresses corresponding to at least one of said scan lines by summing the respective X and Y starting addresses and corresponding first X and Y incremental values and sequentially incrementing said summed read addresses by said first incremental values, on completion of a scan line summing the respective X and Y starting points and corresponding second X and Y incremental values, thereby defining the start of a successive scan line, and sequentially incrementing said read addresses by summing said first and second X and Y incremental values therewith until a predetermined plurality of scan lines defining a frame is completed.
-
Specification