Parallel processing circuits for high speed calculation of the dot product of large dimensional vectors
First Claim
Patent Images
1. A circuit for calculating a(i)·
- b(j) where a(i) is the vector (a,(i), a2 (i) . . . ,aQ (i)),b(j) is the vector (b,(j),b2 (j), . . . bQ (j)), each ak (i) is a zero or a one, and each bk (j) is a zero or a one, comprising;
first memory means for storing digital signals representing a(i);
second memory means for storing digital signals representing b(j);
a first serial-in-parallel-out barrel shift register for creating the bit planes a(o), . . . ,a(N-1) from the digital signals stored in the first memory means;
a second serial-in-parallel-out barrel shift register for creating the bit planes b(o), . . . ,b(N-1) from the digital signals stored in the second memory means;
a first OR gate having a first input connected to the first serial-in-parallel-out barrel shift register;
a second OR gate having a first input connected to the second serial-in-parallel-out barrel shift register;
means for applying a zero or a one to a second input of each of the OR gates;
a correlator connected to an output of the first OR gate and an output of the second OR gate; and
mean connected to the correlator for summing a plurality of successive outputs of the correlator.
4 Assignments
0 Petitions
Accused Products
Abstract
A digital circuit executes a parallel algorithm to compute the dot product of large dimensional vectors at very high speed. The circuit may be made of a plurality of cascaded 1-bit correlator chips and a plurality of ALU chips that sum the output of the correlator chips. Alternatively, a general purpose computer architecture for implementing the invention is also provided.
-
Citations
1 Claim
-
1. A circuit for calculating a(i)·
- b(j) where a(i) is the vector (a,(i), a2 (i) . . . ,aQ (i)),b(j) is the vector (b,(j),b2 (j), . . . bQ (j)), each ak (i) is a zero or a one, and each bk (j) is a zero or a one, comprising;
first memory means for storing digital signals representing a(i); second memory means for storing digital signals representing b(j); a first serial-in-parallel-out barrel shift register for creating the bit planes a(o), . . . ,a(N-1) from the digital signals stored in the first memory means; a second serial-in-parallel-out barrel shift register for creating the bit planes b(o), . . . ,b(N-1) from the digital signals stored in the second memory means; a first OR gate having a first input connected to the first serial-in-parallel-out barrel shift register; a second OR gate having a first input connected to the second serial-in-parallel-out barrel shift register; means for applying a zero or a one to a second input of each of the OR gates; a correlator connected to an output of the first OR gate and an output of the second OR gate; and mean connected to the correlator for summing a plurality of successive outputs of the correlator.
- b(j) where a(i) is the vector (a,(i), a2 (i) . . . ,aQ (i)),b(j) is the vector (b,(j),b2 (j), . . . bQ (j)), each ak (i) is a zero or a one, and each bk (j) is a zero or a one, comprising;
Specification