Elastic buffer for local area networks

• US 4,884,286 A
• Filed: 12/12/1985
• Issued: 11/28/1989
• Est. Priority Date: 12/12/1985
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Szdzepanek, Andre, Buchanan, George
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/808,149
• Time in Patent Office: 1,447 Days
• Field of Search: 375/106, 375/110, 375/118, 328/63, 328/72, 307/269, 365/233, 370/100, 370/102, 370/108
• US Class Current: 375/372
• CPC Class Codes: H04J 3/0626 plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Abstract

An elastic buffer for absorbing frequency jitter or drift of an incoming data signal which includes a serial stack of data register. These data registers are used for storing data bits from an incoming data stream one at a time with each bit adjacent a next earlier bit at a frequency equal to the frequency of the incoming data and also for releasing stored bits onto an output data line. The stored bits are released one at a time at a predetermined fixed rate equal to the average frequency of incoming data from a number of registers away from the register into which data is being written which depends on the frequency difference between incoming data and the fixed rate aforesaid.

Claims

1. An elastic buffer for absorbing frequency jitter or drift of a data stream incoming on an input data line, comprising:

a serial circular stack of data register cells;

means for storing data bits in said cells from an incoming data stream one at a time with each bit in a cell adjacent a cell in which is stored a next earlier bit at a clock frequency BCLK equal to the frequency of arrival of the incoming data;

means for directing stored data from said data registers onto an output data line one at a time at a predetermined fixed clock rate XCLK equal to the average frequency of incoming data;

wherein at any instant the register from which data is taken out is a number of registers away from the register into which data is stored, the number increasing when the frequency of BCLK is greater than that of XCLK and decreasing when the frequency of BCLK is less than that of XCLK;

wherein said directing means includes;

a plurality of output gates each coupled between

the output data line and an output of a corresponding

one of said data registers;

an output pointer circuit selectively coupled to each of said output gates, in turn, at a frequency equal to said average frequency and operable when so coupled to release data from a corresponding one of said data registers onto the data output line;

a plurality of input gates each coupled between

the input data line and an input of a corresponding one of said data registers;

an input pointer circuit selectively coupled to

each of said input gates, in turn, at a frequency equal to the frequency of arrival of the input data and operable when so coupled to open a corresponding input gate and allow transmission of data from said line onto a corresponding data register;

wherein said input and output pointers each

include a plurality of latches, one corresponding to each cell of said data registers, wherein all latches except a selected latch reset to a zero bit while the selected latch resets to a "1" bit and in response to incoming clock signals after each cycle each latch passes its bit level onto a next adjacent latch wherein a "1" level in a given latch causes a control signal to issue to an associated one of the input and output gates of a corresponding data register cell to open the gate and permit a data bit to flow thereby; and

wherein said data register cells each include an ERDET line precharged to a predetermined voltage level, normally non-transmitting gate means connecting said ERDET line to ground, said gate means responsive to a coincident signal from an output pointer latch corresponding to said each cell and from an immediately preceding input pointer latch, and from an input pointer latch corresponding to said each cell and a coincident signal from an immediately preceding output pointer latch to open and ground said ERDET line.

2. An elastic buffer according to claim 1, including a control circuit coupled to said ERDET line having an input set/reset latch, input and output synchronizers coupled in parallel to said latch, said input synchronizer having a input delay circuit followed by a rising edge detector and driver/buffer and said output synchronizer having a output delay circuit followed by a rising edge detector and a driver/buffer wherein the delay of said input delay is obtained from a clock signal BCLK derived from the input data frequency while the output delay is obtained from a fixed clock signal XCLK whose frequency equals the average frequency of the input data and in response to an error signal on said ERDET line to generate an output XPTRCLR from said output synchronizer buffer/driver which resets said output pointer latches and to generate an output BPTRCLR from said input synchronizer buffer/driver which resets said input pointer.

3. An elastic buffer according to claim 2, wherein said output BPTRCLR is coupled to said input set/reset latch and resets the latter and resets said input pointer latches later than the output XPTRCLR resets said output pointer latches.

4. An elastic buffer according to claim 2, including:

means for halting said input pointer circuit in response to a DDSHIFT control signal leaving said output pointer circuit to shift from cell to cell until it is contiguous to the input cell into which data was last shifted at which point an error signal is generated on said ERDET line causing an XPTRCLR output and a BPTRCLR output which reset the output and input pointer circuits, respectively, and in response to which error signal said input pointer circuit restarts after being reset.

5. An elastic buffer according to claim 2, including

a BCOVR line coupled to said input synchronizer at a point at which the signal is complimentary to BPTRCLR and whose phase is in advance thereof;

a BCOVR line coupled to said input synchronizer at a point at which the signal is in phase with BPTRCLR and 1/2 clock cycle later than BCOVR;

a DDTOUT signal line for clearing the input and output pointer circuits;

a latch circuit for storing a selected bit;

a DDTOUT nor circuit having one input coupled to said DDTOUT line and another input coupled to said latch output;

a BCOVR nor circuit having one input coupled to BCOVR and another input coupled to an output of said DDTOUT nor circuit and an output coupled to said latch, wherein the inputs to said DDTOUT nor circuit are clocked by BCLK and those into said latch by NBCLK;

a DDSHIFT gated clock having an input coupled to said latch, pulled up by clock NBCLK and having a DDSHIFT clock output and operative to generate an DDSHIFT output in phase with NBCLK with a "0" bit stored in said latch; and

a SELDIS gated clock having an input coupled through a SELDIS nor gate to said BCOVR line and to said latch and pulled high by BCLK and having a SELDIS clock output and operative to generate a SELDIS output in phase with BCLK when either BCOVR is high or said latch output is low and to stop generating said SELDIS output when a "1" bit is stored in said latch and/or BCOVR is high;

wherein upon BCOVR going low and DDTOUT going high DDSHIFT stops and SELDIS stops at least 1/2 clock cycle later and upon BCOVR going high SELDIS starts and DDSHIFT starts at least 1/2 clock cycle later.

6. An elastic buffer according to claim 3, wherein said input pointer includes a plurality of zero stages and a one stage coupled together in series, each stage having a first clocked transistor for passing an input from a latch circuit of a previous stage to a signal holding circuit on positive cycles of a BCLK clock signal, and a second clocked transistor for transmitting the signal from said signal holding circuit to a latch circuit, a third clocked transistor for transmitting the signal on an output of said latch circuit to an input of a gated clock cicuit, said gated clock having an output coupled to a gate of a transistor coupled between a voltge Vcc and an INPUT REG SELECT line of a corresponding one of said data register cells, a switch coupling said INPUT REG SELECT line to ground in response to a SELDIS clock signal in phase with said BCLK signal, said gated clock upon having a "1" stored in a corresponding latch circuit responsive to following a clock signal NBCLK which is the complement of BCLK and in feeding the clock signal through to its input, a bleeder current source coupled to said INPUT REG SELECT line and reset means responsive to a BPTRCLR signal to reset said associated zero latches to "0" and said one latch to "1".

7. A method of absorbing frequency jitter or drift of an incoming stream of data, comprising:

storing sequentially the data bits in a stack of circularly connected register cells at a clock rate BCLK equal to the frequency of arrival of data bits in said data stream;

directing the stored data bits from said cells one at a time at a fixed clock rate XCLK whose frequency equals the average frequency of incoming data;

wherein at any instant the register from which data is taken out is a number of registers away from the register into which data is stored, which number increases when the frequency of BCLK exceeds that of XCLK and decreases when the frequency of BCLK is less than that of XCLK; and

wherein said steps of storing and directing are operable such that they may occur simultaneously, and wherein each bit may be stored into or directed from any one individual cell within said stack of circularly connected cells.

8. A method according to claim 7, wherein said directing step includes sequentially opening each one of a plurality of output gates controlling the flow of data out of corresponding data register cells.

9. A method according to claim 7, wherein said storing step includes sequentially opening a plurality of input gates each coupled between the input line and an associated data register cell and said directing step includes sequentially opening a plurality of output gates controlling the flow of data out of corresponding data register cells.

10. A method according to claim 8, including sensing when the data register cell into which data is being stored is contiguous with that out of which data is being directed and in the latter event resetting the locations of the data register cells into which data is stored and out of which data is directed to be a predetermined number of said cells apart.

11. A method according to claim 8, including stopping the shifting of the storage position into said data register cells in response to a DDSHIFT control signal and resetting the locations of the data register cells into which data is stored and out of which data is directed to be a predetermined number of said cells apart when the cell out of which data is being directed is contiguous with the last one into which data was stored.