Differential amplifier and current sensing circuit including such an amplifier

• US 4,885,477 A
• Filed: 06/06/1988
• Issued: 12/05/1989
• Est. Priority Date: 06/08/1987
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Armstrong, Desmond R., Bird, Philip H.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/203,404
• Time in Patent Office: 547 Days
• Field of Search: 330/253, 330/257, 330/307, 330/288, 307/497, 307/296.4, 307/296.6, 307/296.8, 323/315, 323/316
• US Class Current: 327/52
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier

Abstract

A differential amplifier includes first and second matched field-effect transistors (FETs) (21,22) having their source electrodes connected together and to a current source (2), and their drain electrodes connected respectively to an input and an output of a current mirror circuit (3). The FETs (21,22) are depletion-mode FETs, and the current source comprises parallel-connected third and fourth depletion-mode FETs (25,26) matched to the first and second FETs (21,22). The current source (2) and current mirror (3) act to constrain the first and second FETs (21,22), to operate over a predetermined operating curve, for which they are optimally matched to one another. The differential amplifier may be constructed as an integrated circuit, and may form part of a circuit for sensing current in a power semiconductor device.

Claims

1. A differential amplifier comprising first and second matched field-effect transistors (FETs) having their source electrodes connected together and to a current source, and their drain electrodes connected respectively to an input and an output of a current mirror circuit, the junction of the output of the current mirror circuit and the drain electrode of the second FET forming a top bar output current of the differential amplifier, characterised in that said first and second FETs are depletion-mode FETs, and in that said current source comprises parallel-connected third and fourth depletion-mode FETs matched to the first and second FETs, each of the third and fourth FETs having its gate and source electrodes connected together and to a voltage supply, and its drain electrode connected to the source electrodes of the first and second FETs.

2. A differential amplifier as claimed in claim 1 comprising switching means for turning off the current mirror circuit from its supply when not in operation so as to reduce current consumption.

3. A differential amplifier as claimed in claim 1 wherein the first, second, third and fourth FETs are integrated on a common substrate.

4. A differential amplifier as claimed in claim 1 or claim 3 wherein the first, second, third and fourth FETs are depletion-mode metal-oxide-semiconductor FETs.

5. A current sensing circuit for sensing an output current of a power semiconductor arrangement, which arrangement has major and minor current carrying sections, each section comprising at least one basic semiconductor element, said major and minor current carrying sections having a common first electrode and corresponding major and minor second electrodes, the current sensing circuit comprising:

means for comparing the voltages at the major and minor second electrodes;

means for controlling a current drawn from the minor second electrode in response to an output of the comparing means so as to cause the voltage at the minor second electrode to end to substantial equality with that at the major second electrode; and

means for measuring the current drawn from the minor second electrode, wherein the comparing means comprises a differential amplifier comprising first and second matched field-effect transistors (FETs) having their source electrodes connected together and to a current source, and their drain electrodes connected respectively to an input and an output of a current mirror circuit, the junction of the output of the current mirror circuit and the drain electrode of the second FET forming a tap for output current of the differential amplifier, characterized in that said first and second FETs are depletion-mode FETs, and in that said current source comprises parallel-connected third and fourth depletion-mode FETs matched to the first and second FETs, each of the third and fourth FETs having its gate and source electrodes connected together and to a voltage supply, and its drain electrode connected to the source electrodes of the first and second FETs, means being provided for coupling the gate electrodes of the first and second FETs respectively to the major and minor second electrodes of the power semiconductor arrangement.

6. A current sensing circuit as claimed in claim 5 wherein the current controlling means comprises a further field-effect transistor having its source electrode arranged for connection to the minor second electrode of the power semiconductor arrangement, its gate electrode connected to the output of the differential amplifier and its drain electrode coupled to the current measuring means.

7. A current sensing circuit as claimed in claim 5, wherein the means for coupling the gate electrodes of the first and second FETs to the second electrodes of the power semiconductor arrangement comprise a pair of potential dividers, each having the same division ratio, each potential divider comprising two depletion-mode FETs, each having its gate electrode connected to its source electrode.

8. A current sensing circuit as claimed in any of claims 5 to 7, wherein said current measuring means includes a threshold detection circuit producing an output signal dependent on the value of the current being measured relative to a predetermined reference level.

9. A current sensing circuit as claimed in any of claims 5 to 7, wherein the current measuring means includes a current mirror means for the current to be measured.

10. A current sensing circuit as claimed in claim 9 wherein means are provided for disabling said current mirror means to reduce current consumption when the current sensing circuit is inoperative.

11. An integrated circuit comprising a power semiconductor arrangement having major and minor current carrying sections, each section comprising at least one basic semiconductor element, said major and minor current carrying sections having a common first electrode and corresponding major and minor second electrodes and a current sensing circuit comprising means for comparing the voltages at the major and minor second electrodes;

means for controlling a current drawn from the minor second electrode in response to an output of the comparing means so as to cause the voltage at the minor second electrode to tend to substantial equality with that at the major second electrode; and

means for measuring the current drawn from the minor second electrode, wherein the comparing means comprises a differential amplifier comprising first and second matched field-effect transistors (FETs) having their source electrodes connected together and to a current source, their gate electrodes coupled respectively to said major and minor second electrodes, and their drain electrodes connected respectively to an input and an output of a current mirror circuit, the junction of the output of the current mirror circuit and the drain electrode of the second FET forming a tap for output current of the differential amplifier, characterized in that said first and second FETs are depletion-mode FETs, and in that said current source comprises parallel-connected third and fourth depletion-mode FETs matched to the first and second FETs, each of the third and fourth FETs having its gate and source electrodes connected together and to a voltage supply, and its drain electrode connected to the source electrodes of the first and second FETs.

12. A integrated circuit as claimed in claim 11, in which the power semiconductor arrangement comprises a metal-oxide-semiconductor power transistor having a plurality of cells having a common drain terminal comprising said common first electrode, and a common gate terminal, the major current carrying section comprising a majority of said cells having a common major source terminal comprising said major second electrode, and the minor current carrying section comprising at least one of said cells having a minor source terminal comprising said minor second electrode.