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Method and apparatus for efficiently handling temporarily cacheable data

  • US 4,885,680 A
  • Filed: 07/25/1986
  • Issued: 12/05/1989
  • Est. Priority Date: 07/25/1986
  • Status: Expired due to Term
First Claim
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1. In a high speed electronic multiprocessor computer system comprising a plurality of separate processing elements (PE), each having associated therewith a high speed cache memory and a large shared main memory accessible to each PE and its, associated cache, and to other PE'"'"'s and caches in the system, each cache memory including a control mechanism and a cache directory accessible to its local PE said cache directory containing the addresses of all data lines currently stored in the cache memory, said cache memory and main memory being operable under the control of a memory management procedure including a method for managing temporarily cacheable data resident in each cache serving its associated processor in which each processor can invalidate the temporarily cacheable data in its associated cache with a single instruction, said instruction being applied to temporarily cacheable data independently of the ranges of addresses of the temporarily cacheable data, the method comprisingassociating a marked data bit (MDB) field with a data line of temporarily cacheable data, through the steps ofaccessing a data line from main memory after a cache miss,concurrently accessing the associated marked data bit (MDB) field which indicates that the data line to which the MDB refers is temporarily cacheable data when the MDB is set to a first binary state,storing said MDB in the cache directory at the line address where the data line referenced by the MDB is stored, andselectively invalidating all lines in the cache having their MDBs set to said first binary state in response to a single invalidate MDB instruction received from the PE which is served by the particular cache memory.

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