Method and apparatus for efficiently handling temporarily cacheable data
First Claim
1. In a high speed electronic multiprocessor computer system comprising a plurality of separate processing elements (PE), each having associated therewith a high speed cache memory and a large shared main memory accessible to each PE and its, associated cache, and to other PE'"'"'s and caches in the system, each cache memory including a control mechanism and a cache directory accessible to its local PE said cache directory containing the addresses of all data lines currently stored in the cache memory, said cache memory and main memory being operable under the control of a memory management procedure including a method for managing temporarily cacheable data resident in each cache serving its associated processor in which each processor can invalidate the temporarily cacheable data in its associated cache with a single instruction, said instruction being applied to temporarily cacheable data independently of the ranges of addresses of the temporarily cacheable data, the method comprisingassociating a marked data bit (MDB) field with a data line of temporarily cacheable data, through the steps ofaccessing a data line from main memory after a cache miss,concurrently accessing the associated marked data bit (MDB) field which indicates that the data line to which the MDB refers is temporarily cacheable data when the MDB is set to a first binary state,storing said MDB in the cache directory at the line address where the data line referenced by the MDB is stored, andselectively invalidating all lines in the cache having their MDBs set to said first binary state in response to a single invalidate MDB instruction received from the PE which is served by the particular cache memory.
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Abstract
A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved. The bit is passed to the cache together with the associated real address after address translation (in the case of a real cache). when the cache controls load the address of the data in the directory it is also stored the marked data bit (MDB) in the directory with the address. When the cacheability of the temporarily cacheable data changes from cacheable to non-cacheable, a single instruction is issued to cause the cache to invalidate all marked data. When an "invalidate marked data" instruction is received, the cache controls sweep through the entire cache directory and invalidate any cache line which has the "marked data bit" set in a single pass. An extension of the invention involves using a multi-bit field rather than a single bit to provide a more versatile control of the temporary cacheability of data.
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Citations
18 Claims
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1. In a high speed electronic multiprocessor computer system comprising a plurality of separate processing elements (PE), each having associated therewith a high speed cache memory and a large shared main memory accessible to each PE and its, associated cache, and to other PE'"'"'s and caches in the system, each cache memory including a control mechanism and a cache directory accessible to its local PE said cache directory containing the addresses of all data lines currently stored in the cache memory, said cache memory and main memory being operable under the control of a memory management procedure including a method for managing temporarily cacheable data resident in each cache serving its associated processor in which each processor can invalidate the temporarily cacheable data in its associated cache with a single instruction, said instruction being applied to temporarily cacheable data independently of the ranges of addresses of the temporarily cacheable data, the method comprising
associating a marked data bit (MDB) field with a data line of temporarily cacheable data, through the steps of accessing a data line from main memory after a cache miss, concurrently accessing the associated marked data bit (MDB) field which indicates that the data line to which the MDB refers is temporarily cacheable data when the MDB is set to a first binary state, storing said MDB in the cache directory at the line address where the data line referenced by the MDB is stored, and selectively invalidating all lines in the cache having their MDBs set to said first binary state in response to a single invalidate MDB instruction received from the PE which is served by the particular cache memory.
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17. In a high speed electronic multiprocessor computer system comprising a plurality of separate processing elements (PE), each having associated therewith a high speed real cache memory including a control mechanism and a cache directory accessible to its local PE, said cache directory containing the real addresses of all data lines currently stored in the cache memory and a large shared main memory accessible to each PE, its associated cache, and other PE'"'"'s and caches in the system said system including a dynamic addressing facility including page and segment mapping tables in memory and a translation Look-aside Buffer (TLB) for storing recent address translations of virtual addresses and wherein the fact that data is temporarily cacheable is determined during compilation of a particular program and stored as a marked data bit field (MDB) in the segment and page mapping tables, a method for managing temporarily cacheable data resident in the cache which includes accessing from the segment and page mapping tables in memory or the TLB, the marked data bit (MDB) field, for indicating that a data line to which the MDB refers is temporarily cacheable data, and storing said MDB field in the cache directory when an associated data line is stored in the cache,
storing the MDB associated with a particular address in the mapping tables in the TLB together with a translation of the address following a TLB miss, searching through the entire cache directory without regard to the memory address of the data in response to a single invalidate MDB instruction to detect all cache lines having their MDBs set to a predetermined state to indicate temporary cacheability and, setting all detected lines to an invalid status signifying that the data cannot be used.
Specification