Improved logic cell array using CMOS E.sup.2 PROM cells

• US 4,885,719 A
• Filed: 08/19/1987
• Issued: 12/05/1989
• Est. Priority Date: 08/19/1987
• Status: Expired due to Term

• Current Assignee: Analog Technologies Incorporated
• Original Assignee: ICT International CMOS Technology Incorporated
• Inventors: Brahmbhatt, Dhaval J.
• Primary Examiner(s): Gossage, Glenn A.
• Application Number:
  US07/087,143
• Time in Patent Office: 839 Days
• Field of Search: 365/184, 365/185, 365/182, 365/181, 307/465, 307/469, 307/468, 364/716, 340/825.79, 340/825.83, 340/825.85, 340/825.86, 340/825.87, 340/825.90, 340/825.91, 340/825.93, 357/23.5
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A programmable memory cell useful in a logic cell array draws no D.C. power in either a "1" or a "0" state. The cell includes a CMOS transistor pair including a p-channel transistor connected to a positive voltage source and an n-channel transistor connected to a circuit ground potential. The cell output is connected to a common terminal of the CMOS transistor pair. The CMOS transistor pair has a common floating gate which is selectively charged for programming the cell. In a preferred embodiment, the floating gate comprises a first polycrystalline silicon layer (polysilicon), and capacitive means including a second polysilicon layer spaced from and capacitively coupled with the first polysilicon layer is utilized to selectively applying charge to the common floating gate.

Claims

1. A logic cell array comprising a plurality of configurable logic blocks arranged in rows and columns, each logic block including an electrically erasable programmable memory cell (E² PROM), said cell having a series connected CMOS transistor pair including a p-channel transistor having a source terminal connected to a positive voltage source and an n-channel transistor having a drain terminal connected a circuit ground potential, an output connected to a common terminal of said CMOS transistor pair, said CMOS transistor pair having a common floating gate, and means for selectively charging said common floating gate including capacitive means coupled to said floating gate, a programming electrode, a tunnelling oxide separating said programming electrode and said floating gate, and a programming transistor connected to said programming electrode for applying a programming voltage to said programming electrode for cold electron injection through said tunnelling oxide to said common floating gate.

2. The logic cell array as defined by claim 1 wherein said common floating gates comprises a first polycrystalline silicon layer and said capacitive means includes a second polycrystalline silicon layer spaced from, and capacitively coupled with, said first polycrystalline silicon layer.

3. An electrically erasable programmable memory cell (E² PROM) comprising a series connected CMOS transistor pair including a p-channel transistor having a source terminal connected to a positive voltage source and an n-channel transistor having a drain terminal connected to a circuit ground potential, an output connected to a common terminal of said CMOS transistor pair, said CMOS transistor pair having a common floating gate, and means for selectively charging said common floating gate including capacitive means coupled to said floating gate, a programming electrode, a tunnelling oxide separating said programming electrode and said floating gate, and a programming transistor connected to said programming electrode for applying a programming voltage to said programming electode for cold electron injection through said tunnelling oxide to said common floating gate.

4. The program memory cell as defined by claim 3 wherein said common floating gate comprises a first layer of polycrystalline silicon material and said capacitive means comprises a second layer of polycrystalline silicon material spaced from, and capacitively coupled with, said first polycrystalline silicon material.