Communication system

• US 4,887,266 A
• Filed: 12/29/1986
• Issued: 12/12/1989
• Est. Priority Date: 04/29/1985
• Status: Expired due to Fees

• Current Assignee: Process Automation & Computer Systems Limited
• Original Assignee: Process Automation & Computer Systems Limited
• Inventors: Lawrence, Peter J., Owen, Lyndon N., Neve, Brian D.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Scutch, III, Frank M.
• Application Number:
  US07/002,763
• Time in Patent Office: 1,079 Days
• Field of Search: 370/95, 370/96, 370/89, 370/90, 340/825.08
• US Class Current: 370/349
• CPC Class Codes: H04B 7/269 Master/slave synchronisation
• CPC Class Codes: H04Q 9/00 Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
• CPC Class Codes: H04W 88/08 Access point devices
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A communication system able to provide multiple path communication between a plurality of stations operating on a single channel. The stations are synchronized and a cyclically repeating series of time slots is defined. One time slot in each cycle is reserved for the transmission of synchronization information by a station designated the master station for reception by the other stations, designated slave stations, and maintaining synchronization therein. Another time slot is reserved for any slave station to transmit a message that it requires to communicate to another station, such indication preferably being by transmitting its own pre-assigned address code. The remaining time slots are used for transmitting address information and data. The slave stations operate in a low power condition except during one of the other time slots when they may receive their own address, or except when they need to transmit data.

Claims

1. A communication system operating on a single channel including a device at each of a plurality of nodes between which it is desired to establish communication, one device including means for transmitting synchronization information to each other device simultaneously and each other device having means for providing a synchronization signal in synchrony with said synchronization information, said one device being capable of transmitting to each other device simultaneously an address of another device in one of a cyclically repeating series of consecutive time slots, said one time slot being preassigned for transmission of said address and said other device being arranged to communicate upon receipt and recognition of its address, and at least one other of said time slots in each cycle being reserved so that no such said address may be transmitted therein, whereby any of said other devices may transmit in such a reserved time slot to request communication on said channel, the remaining time slots of said series being usable for the transmission of address information and data.

2. A communication system as claimed in claim 1 wherein each said other device has a pre-assigned address and operates to decode transmitted information on said channel only in a particular time slot dependent on said address.

3. A communication system as claimed in claim 2 wherein a said other device is arranged to transmit its address in said reserved time slot when it requests communication.

4. A communication system as claimed in claim 1 wherein every word of data which passes between said devices is accompanied by at least one bit of link control information, and each device includes a register for holding information indicative of the current mode of operation of the device and is arranged to combine the link control information with the contents of the register to control the subsequent operation.

5. A communication system as claimed in claim 1 including radio transmitter and receiver apparatus for providing data communication with an electrical apparatus, comprising a transmitter circuit, a receiver circuit and an interface circuit, said interface circuit including a processor controlled by a stored program and being arranged to control the transfer of data from said electrical apparatus to the transmitter circuit and/or from the receiver circuit to the electrical apparatus, and said interface circuit being operable in a condition in which data transfer can take place or in a lower power consumption condition in which data transfer cannot take place, the interface circuit being operable automatically to enter the lower power condition when a communication operation has been completed and automatically to re-enter the data transfer condition when a signal is received from the electrical apparatus indicative of the need to transmit data and when a predetermined code signal is received by the receiver circuit indicative of the need to receive data.

6. A communication system as claimed in claim 5 wherein the interface circuit includes a microprocessor which is operable in a lower power condition.

7. A communication system as claimed in claim 5 wherein the power supply to the transmitter circuit may be controlled by the interface circuit, the interface circuit being arranged to energize the transmitter circuit only when transmission is required.

8. A communication system as claimed in claim 1 comprising a plurality of stations each having a transmitter, a receiver, a control processor and a buffer store for data to be transmitted, the control processor being responsive to the state of fullness of the buffer and arranged in dependence thereon to cause an alteration in the rate of data flow through the system.

9. A communication system as claimed in claim 8 wherein every word of data which passes through the system is accompanied by at least one bit of link control information, and each control processor includes a register for holding information indicative of the current mode of operation of the station and is arranged to combine the link control information with the contents of the register to control the subsequent operation, to provide at least a mode of increased rate of data throughput when the state of fullness of the buffer so dictates.

10. A communication system as claimed in claim 8 wherein the system is a synchronous communication system with one station designated the master station providing system synchronization signals, and defining a cyclic sequence of time slots comprising at least one synchronization time slot, at least one interrupt time slot, and a plurality of address or data time slots, wherein any other station can transmit a message to the master station during an interrupt time slot to indicate a request to communicate.

11. A communication system as claimed in claim 10 wherein after the master station has acknowledged the request to communicate a station may transmit to the master station the address of the destination station if this is not known to the master station, the master station being arranged then to broadcast a signal to the source and destination stations allocating them a time slot for communication.

12. A communication system as claimed in claim 11 wherein after the allocation of the time slot data transfer takes place and if the accompanying link control information indicates that the buffer of the source station is not empty, the master station automatically allocates further time on the transmission channel.