Process for making a contact structure including polysilicon and metal alloys
First Claim
1. A method of fabricating a field effect transistor integrated circuit structure wherein a layer of polycrystalline silicon is formed over a silicon body covered by a first layer of silicon dioxide, said polycrystalline silicon layer being masked in areas where a gate electrode is desired and etched in unmasked areas of said polycrystalline silicon, comprising the steps of:
- forming a second layer of silicon dioxide over said masked and unmasked areas,selectively etching said first and second silicon dioxide layers for exposing source and drain regions adjacent said gate electrode,doping said exposed source and drain regions with a dopant,forming a third layer of silicon dioxide over said source and drain regions and said gate electrode,forming contact windows to said gate electrode, said source and drain regions, and said silicon body, wherein said contact window to said source and drain regions also expose portions of said silicon body,forming a polycrystalline silicon layer over said gate electrode, said source and drain regions, and said exposed portions of said silicon body, wherein said polycrystalline silicon layer contacts exposed regions of said gate electrode, said source and drain regions, and said silicon body,doping said polycrystalline silicon layer with an impurity, diffusing said impurity into said polycrystalline silicon layer and into said silicon body,depositing a first refractory metal alloy layer over said polycrystalline silicon layer, said refractory metal alloy layer comprising approximately 10 to 30 percent by weight Tungsten,depositing a second refractory metal alloy layer over said first refractory metal alloy layer, said second refractory metal alloy layer comprising at least 70 percent by weight Tungsten,depositing an interconnect metal layer over said refractory metal alloy layers and,heating said integrated circuit structure to a temperature of at least approximately 400 degrees Celsius but less than a temperature required to form a metallic silicide layer comprising silicon from either said polysilicon layer or said silicon body.
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Abstract
A multi-layer contact process is described for providing contact to a shallow semiconductor region forming a semiconductor PN junction and with a silicon semiconductor body. The multi-layer structure includes a layer of polycrystalline silicon doped with an impurity of the same conductivity type as that of the semiconductor region. A first layer of a refractory alloy is deposited over the polycrystalline silicon layer to provide electrically stable interface therewith. A second layer of another refractory metal or alloy is deposited over the first refractory metal alloy layer and serves to protect the shallow PN junction against current leakage failure. A third layer of interconnect metal is deposited over the multi-layer contact structure. The resulting structure provides a low resistance ohmic contact to a shallow semiconductor region with improved electrical characteristics.
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Citations
5 Claims
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1. A method of fabricating a field effect transistor integrated circuit structure wherein a layer of polycrystalline silicon is formed over a silicon body covered by a first layer of silicon dioxide, said polycrystalline silicon layer being masked in areas where a gate electrode is desired and etched in unmasked areas of said polycrystalline silicon, comprising the steps of:
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forming a second layer of silicon dioxide over said masked and unmasked areas, selectively etching said first and second silicon dioxide layers for exposing source and drain regions adjacent said gate electrode, doping said exposed source and drain regions with a dopant, forming a third layer of silicon dioxide over said source and drain regions and said gate electrode, forming contact windows to said gate electrode, said source and drain regions, and said silicon body, wherein said contact window to said source and drain regions also expose portions of said silicon body, forming a polycrystalline silicon layer over said gate electrode, said source and drain regions, and said exposed portions of said silicon body, wherein said polycrystalline silicon layer contacts exposed regions of said gate electrode, said source and drain regions, and said silicon body, doping said polycrystalline silicon layer with an impurity, diffusing said impurity into said polycrystalline silicon layer and into said silicon body, depositing a first refractory metal alloy layer over said polycrystalline silicon layer, said refractory metal alloy layer comprising approximately 10 to 30 percent by weight Tungsten, depositing a second refractory metal alloy layer over said first refractory metal alloy layer, said second refractory metal alloy layer comprising at least 70 percent by weight Tungsten, depositing an interconnect metal layer over said refractory metal alloy layers and, heating said integrated circuit structure to a temperature of at least approximately 400 degrees Celsius but less than a temperature required to form a metallic silicide layer comprising silicon from either said polysilicon layer or said silicon body. - View Dependent Claims (2, 3, 4, 5)
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Specification