Process for making a contact structure including polysilicon and metal alloys

• US 4,888,297 A
• Filed: 10/20/1987
• Issued: 12/19/1989
• Est. Priority Date: 09/20/1982
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tsang, Yuk L., Aboelfotoh, Mohamed O.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): QUACH, TUAN N
• Application Number:
  US07/110,996
• Time in Patent Office: 791 Days
• Field of Search: 437/200, 437/193, 437/40, 437/41, 437/42, 437/43, 437/44, 437/45, 437/192, 437/162, 437/246, 156/643, 156/653, 357/23.1, 357/23.8, 357/54, 148/DIG. 131, 148/DIG. 20
• US Class Current: 438/307
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/02 Contacts, special

Abstract

A multi-layer contact process is described for providing contact to a shallow semiconductor region forming a semiconductor PN junction and with a silicon semiconductor body. The multi-layer structure includes a layer of polycrystalline silicon doped with an impurity of the same conductivity type as that of the semiconductor region. A first layer of a refractory alloy is deposited over the polycrystalline silicon layer to provide electrically stable interface therewith. A second layer of another refractory metal or alloy is deposited over the first refractory metal alloy layer and serves to protect the shallow PN junction against current leakage failure. A third layer of interconnect metal is deposited over the multi-layer contact structure. The resulting structure provides a low resistance ohmic contact to a shallow semiconductor region with improved electrical characteristics.

Claims

1. A method of fabricating a field effect transistor integrated circuit structure wherein a layer of polycrystalline silicon is formed over a silicon body covered by a first layer of silicon dioxide, said polycrystalline silicon layer being masked in areas where a gate electrode is desired and etched in unmasked areas of said polycrystalline silicon, comprising the steps of:

forming a second layer of silicon dioxide over said masked and unmasked areas,

selectively etching said first and second silicon dioxide layers for exposing source and drain regions adjacent said gate electrode,

doping said exposed source and drain regions with a dopant,

forming a third layer of silicon dioxide over said source and drain regions and said gate electrode,

forming contact windows to said gate electrode, said source and drain regions, and said silicon body, wherein said contact window to said source and drain regions also expose portions of said silicon body,

forming a polycrystalline silicon layer over said gate electrode, said source and drain regions, and said exposed portions of said silicon body, wherein said polycrystalline silicon layer contacts exposed regions of said gate electrode, said source and drain regions, and said silicon body,

doping said polycrystalline silicon layer with an impurity, diffusing said impurity into said polycrystalline silicon layer and into said silicon body,

depositing a first refractory metal alloy layer over said polycrystalline silicon layer, said refractory metal alloy layer comprising approximately 10 to 30 percent by weight Tungsten,

depositing a second refractory metal alloy layer over said first refractory metal alloy layer, said second refractory metal alloy layer comprising at least 70 percent by weight Tungsten,

depositing an interconnect metal layer over said refractory metal alloy layers and,

heating said integrated circuit structure to a temperature of at least approximately 400 degrees Celsius but less than a temperature required to form a metallic silicide layer comprising silicon from either said polysilicon layer or said silicon body.

2. A method of fabricating a field effect transistor as in claim 1 wherein:

an N-type dopant, dopes said exposed source and drain regions.

3. A method of fabricating a field effect transistor as in claim 1 wherein:

an N-type impurity dopes said polycrystalline silicon layer.

4. A method of fabricating a field effect transistor as in claim 1 wherein:

a P-type dopant, dopes said exposed source and drain regions.

5. A method of fabricating a field effect transistor as in claim 1 wherein:

a P-type impurity dopes said polycrystalline silicon layer.