Routing among field effect transistors

• US 4,888,299 A
• Filed: 02/21/1989
• Issued: 12/19/1989
• Est. Priority Date: 02/26/1988
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd., Hitachi Vlsi Engineering Corporation
• Original Assignee: Hitachi, Ltd., Hitachi Vlsi Engineering Corporation
• Inventors: Ono, Kunio, Shiraishi, Yoichi, Naka, Ichiro, Sakemi, Junya
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): THOMAS, TOM
• Application Number:
  US07/313,627
• Time in Patent Office: 301 Days
• Field of Search: 437/51, 437/189, 437/195, 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/130
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Interconnections interconnecting terminals to be connected by routings are dissolved into two-terminal interconnections and it is determined to which kind of terminals the terminals of each two-terminal interconnection belong, among connected diffusion layer, separated diffusion layer and gate. The interconnections are classified into groups by the combination of the kind of two terminals for each interconnection. The respective groups of interconnections are routed in the channel on the field effect transistor row according to a predetermined order of groups.

Claims

1. A method of routing terminals of field effect transistors in a cell having at least two field effect transistor rows each having a fixed transverse length, channels on said field effect transistor rows where single wiring layer can be used, a channel sandwiched between each pair of said field effect transistor rows, and having a fixed transverse length where double wiring layers can be used, and channels outside the field effect transistor rows where double wiring layers can be used, by using a feedthrough or feedthroughs traversing across the field effect transistor row for interconnecting the routings in these channels and by interconnecting diffusion layers and gates which are the terminals of the field effect transistors, comprising the steps of:

dissolving given interconnections into two-terminal interconnections;

selecting as many two-terminal interconnections from said dissolved two-terminal interconnections as possible provided that the respective selected two-terminal interconnections do not cause any shortcircuit;

providing selection criteria of interconnection in routing on a wirable region of a channel on the field effect transistor row, selecting two-terminal interconnections to be routed in the channel on the field effect transistor row according to the criteria and routing the selected two-terminal interconnections;

making a feedthrough for a non-selected two-terminal interconnection and routing the non-selected interconnection; and

finally routing two-terminal interconnections in the channels where double wiring layers can be used.

2. A method of routing terminals of field effect transistors according to claim 1, wherein said criteria includes classifying the two-terminal interconnections into

(a) two terminal interconnection interconnecting a pair of connected diffusion layers each of which is merged with an adjacent diffusion layer of an adjacent field effect transistor which is to be held at the same potential;

(b) two-terminal interconnection interconnecting a connected diffusion layer and a separated diffusion layer which cannot be merged with an adjacent diffusion layer of an adjacent field effect transistor because of a different potential to be applied thereto;

(c) two-terminal interconnection interconnecting a separated diffusion layer and another separated diffusion layer;

(d) two-terminal interconnection interconnecting a connected diffusion layer and a gate;

(e) two-terminal interconnection interconnecting a separated diffusion layer and a gate; and

(f) two-terminal interconnection interconnecting a gate and another gate, and selecting two-terminal interconnections to be routed in the channel on the field effect transistor row according to the above-described order.

3. A method of routing terminals of field effect transistors according to claim 1, wherein said criteria include classifying two-terminal interconnections into

(a) two-terminal interconnection interconnecting a separated diffusion layer which is not merged with an adjacent diffusion layer of an adjacent field effect transistor because of a different potential to be applied thereto, and a connected diffusion layer which is merged with an adjacent diffusion layer of an adjacent field effect transistor which is to be held at the same potential;

(b) two-terminal interconnection interconnecting a pair of connected diffusion layers;

(c) two-terminal interconnection interconnecting a pair of separated diffusion layers;

(d) two-terminal interconnection interconnecting a connected diffusion layer and a gate;

(e) two-terminal interconnection interconnecting a separated diffusion layer and a gate;

(f) two-terminal interconnection interconnecting a pair of gates,

and selecting two-terminal interconnections to be routed in the channel on the field effect transistor row according to the above-described order.

4. A method of routing terminals of field effect transistors according to claim 1, wherein said criteria include classifying two-terminal interconnections into

(a) two-terminal interconnection interconnecting a pair of connected diffusion layers each of which is merged with an adjacent diffusion layer of an adjacent field effect transistor which is to be held at the same potential;

(b) two-terminal interconnection interconnecting a separated diffusion layer which is not merged with an adjacent diffusion layer of an adjacent field effect transistor because of a different potential to be applied thereto, and a connected diffusion layer;

(c) two-terminal interconnection interconnecting a pair of separated diffusion layers;

(d) two-terminal interconnection interconnecting a separated diffusion layer and a gate;

(e) two-terminal interconnection interconnecting a connected diffusion layer and a gate;

(f) two-terminal interconnection interconnecting a pair of gates,

and selecting two-terminal interconnections to be routed in the channel on the field effect transistor row according to the above-described order.

5. A method of routing terminals of field effect transistors according to claim 1, wherein said criteria includes classifying two-terminal interconnections into

(a) two-terminal interconnection interconnecting a separated diffusion layer which is not merged with an adjacent diffusion layer of an adjacent field effect transistor because of a different potential to be applied thereto, and a connected diffusion layer which is merged with an adjacent diffusion layer of an adjacent field effect transistor which is to be held at the same potential;

(b) two-terminal interconnection interconnecting a pair of connected diffusion layers;

(c) two-terminal interconnection interconnecting a pair of separated diffusion layers;

(d) two-terminal interconnection interconnecting a separated diffusion layer and a gate;

(e) two-terminal interconnection interconnecting a connected diffusion layer and a gate;

(f) two-terminal interconnection interconnecting a pair of gates,

and selecting two-terminal interconnections to be routed in the channel on the field effect transistor row according to the above-described order.