Memory control system

• US 4,888,687 A
• Filed: 05/04/1987
• Issued: 12/19/1989
• Est. Priority Date: 05/04/1987
• Status: Expired due to Fees

• Current Assignee: Computervision Corp. (PTC Inc.)
• Original Assignee: Prime Computer, Inc. (DR Holdings, Inc. of Delaware)
• Inventors: Allison, Robert, Lefsky, Brian
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US07/046,456
• Time in Patent Office: 960 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection

Abstract

A system for controlling the addressing of a memory on a predetermined multi-megabyte decode boundary. An address shifter is coupled between CPU address lines and backplane area bussed address lines. The address shifter is controlled in accordance with the control signal determined by the memory array of largest capacity of all memory arrays. The control signal has different states to control the address shifter to couple different address bit patterns therethrough to the backplane area address bus as a function of the selected control signal state.

Claims

1. A memory control system for controlling addressing of memory arrays in a computer system which can accept memory arrays of various storage capacity, each memory array including multiple array banks, said memory arrays coupled to a memory backplane area of said computer system having a plurality of connectors corresponding to said plurality of memory arrays, and said memory backplane coupled to an input address bus through said memory control system, said memory control system comprising;

address shifter means including multiplexer means having a plurality of segments, each segment coupled to receive a plurality of input address lines of said input address bus and having an address output, said multiplexer means having a control input, means for establishing a control signal determined by the largest memory array in the backplane, means for decoupling the address output of each multiplexer means segment to a corresponding backplane connector, said multiplexer means placing at said address output of each segment said plurality of input address lines of said input address bus in accordance with said control signal such that proper memory addressing is established.

2. A memory control system as set forth in claim 1 wherein said backplane connectors accommodate arrays of at least four megabyte and eight megabyte capacity.

3. A memory control system as set forth in claim 2 wherein said memory arrays comprise both four megabyte and eight megabyte arrays and wherein said control signal to the multiplexer means corresponds to a largest memory array of eight megabytes.

4. A memory control system as set forth in claim 3 wherein the control signal causes a shift in address signals by at least one address position when changing control from a four megabyte decode to an eight megabyte decode.

5. A memory control system as set forth in claim 4 wherein the backplane has a backplane address bus including at least one address bit for bank decode and three address bits for array decode.

6. A memory control system as set forth in claim 5 wherein each array bank has multiple word locations, each word location comprising multiple bytes.

7. A memory control system as set forth in claim 6 wherein the backplane address bus also includes address bits for word decode and address bits for byte decode.

8. A memory control system as set forth in claim 1 wherein the control signal to the multiplexer means causes a shift in address signals by at least one address position when changing control from one largest capacity memory array to a different largest capacity memory array.

9. A memory control system as set forth in claim 1 wherein said means for establishing a control signal includes selection means at said memory backplane.

10. A memory control system as set forth in claim 9 wherein said means for controlling the multiplexer means in accordance with the selection means includes means for providing a binary control signal to said multiplexer means.

11. A memory control system as set forth in claim 10 wherein the binary control signal has two control bits for providing up to four different address selections by the multiplexer up to four different address selections by the multiplexer means.

12. A memory control system as set forth in claim 11 wherein said selection means includes jumper means.

13. A memory control system as set forth in claim 12 wherein the backplane area has means defining a predetermined slot code for identifying each particular memory array.

14. A memory control system as set forth in claim 13 including comparator means associated with each memory array and having first and second address inputs to be compared and means coupling the slot code to the first address inputs of the comparator means and means coupling backplane area address signals to the second address inputs of the comparator means, said comparator means providing an output array select signal upon equal comparison.

15. A memory control system as set forth in claim 14 wherein said input address bus couples from a processing unit, and further including means for coupling the array select signal to the processing means to monitor said signal.

16. A memory control system as set forth in claim 15 further including a bank decoder for receiving at least one backplane area address signal to provide an output bank select signal.

17. A memory control system as set forth in claim 16 wherein the bank decoder has the capability of decoding two backplane area address signals.

18. A memory control system as set forth in claim 17 further including coupling means having one position for coupling a predetermined address signal to said bank decoder and another position for coupling said predetermined address signal to said comparator means.

19. A memory control system as set forth in claim 18 wherein said coupling means includes jumper means.

20. A system for controlling the addressing of a memory on a predetermined multi-megabyte decode boundary, said system including a processing means having a processor address bus comprising a plurality of address lines, a backplane area having a backplane area address bus, also having a plurality of address lines, said memory comprising a plurality of memory arrays, means coupling the memory arrays to the backplane area address bus, memory address controller means, and means coupling said memory address controller means for shifting address signals between said processor address bus and backplane area address bus, said memory address controller means comprising, address shifter means for shifting address signals having input terminals coupled to said address lines of said processor address bus and output terminals coupled to said backplane area address bus and further having a control input, means for establishing a control signal determined by the memory array of largest capacity of all m emory arrays, said control signal having different states to control said address shifter means to couple different address line patterns therethrough to said backplane area address bus as a function of the selected control signal state.

21. A system as set forth in claim 20 wherein said address line patterns to said backplane area address bus comprise higher order address lines as the capacity of the largest capacity array increases.

22. A system as set forth in claim 21 wherein the array memory capacity may be one of N megabyte and 2N megabyte.

23. A system as set forth in claim 22 wherein said address line patterns to said backplane area address bus shift upwardly by one address line as the largest capacity memory increase from N megabytes to 2N megabytes.

24. A system as set forth in claim 20 wherein said address shifter means comprises a multiplexer means.

25. A system as set forth in claim 24 further including means defining a predetermined array code for identifying each particular memory array and comparator means for comparing the array identifying code with the backplane area address lines, said backplane area address lines indicating the array containing the accessed address and outputting an array select signal if a match is detected.

26. A system as set forth in claim 25 further including a bank decoder for receiving at least one backplane area address signal to provide an output bank select signal.

27. A system as set forth in claim 26 further including coupling means having one position for coupling a predetermined address signal to said bank decoder and another position for coupling said predetermined address signal to said comparator means.

28. A system as set forth in claim 27 wherein said coupling means includes jumper means.

29. A method of controlling the addressing of a memory on a predetermined multi-megabyte decode boundary in which the memory is sectioned into a plurality of memory arrays, said method comprising the steps of, providing a backplane area with an address bus having a plurality of address lines, coupling said memory arrays to said address lines of said backplane area, providing a processing means having a processor address bus comprising a plurality of address lines which are coupled to said backplane, establishing a control signal determined by the memory array of largest capacity of all memory arrays, and shifting the coupling of the address lines from the processor address bus to the backplane area address bus under control of said control signal so as to couple different address patterns to the backplane area address bus as a function of the largest capacity memory array.

30. A method as set forth in claim 29 wherein the address bits shift to higher order address bits as the capacity of the largest capacity array increases.

31. A method as set forth in claim 29 further providing a predetermined array code for identifying each particular memory array and comparing the array identifying code with the backplane area address bits to provide an output array select signal.

32. A method as set forth in claim 31 further decoding at least one backplane area address signal to provide an output bank select signal.