Semiconductor test system

• US 4,888,715 A
• Filed: 11/19/1985
• Issued: 12/19/1989
• Est. Priority Date: 12/03/1984
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Matsui, Hideo, Tada, Tetsuo
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Ramirez, Ellis B.
• Application Number:
  US06/799,726
• Time in Patent Office: 1,491 Days
• Field of Search: 324/158 R, 324/73 R, 324/73 AT, 324/73 PC, 324/158 F, 324/158 T, 371/25, 371/27, 371/16, 371/20, 371/15, 371/21, 371/29, 364/550, 364/579, 364/580
• US Class Current: 714/736
• CPC Class Codes: G01R 31/31935 Storing data, e.g. failure memory
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence

Abstract

A semiconductor test system comprises an expected value storage area for storing expected values of output data supplied from a semiconductor device under test, a memory device for storing output data directly supplied from the semiconductor device under test in the form of the identical code with that of the expected value storage area, and a comparator for comparing output data from the memory device directly with expected values from the expected value storage area without any conversion.

Claims

1. A semiconductor test system for testing functions of a semiconductor device and evaluating the same, said semiconductor test system comprising:

first storage means for storing all the output data signals supplied from said semiconductor device to be tested, said semiconductor device operating along a predetermined procedure;

second storage means for storing said predetermined procedure in the form identical to internal machine code specific to said semiconductor device to be tested and for directly supplying said predetermined procedure to said semiconductor device to be tested;

expected value storage means for storing expected values of said all of the output data to be supplied from said semiconductor device to be tested in the form of codes identical to those stored in said first storage means; and

comparator means for directly receiving all the output data signals from said first storage means and said expected value storage means to compare the same with each other to determine whether or not said device is faulty.

2. A semiconductor test system in accordance with claim 1, further including third storage means for storing a test program supplying said predetermined procedure in the form of a programming language and means for writing said predetermined procedure in said first storage means along a test program from said third storage means.

3. A semiconductor test system for testing functions of a microprocessor or microcomputer under test comprising:

first storage means for storing machine codes supplied from performance of said functions by said microprocessor or microcomputer under test, said microprocessor or microcomputer operating along a predetermined procedure;

expected machine code storage means for storing expected machine codes to be supplied from performance of said functions by said microprocessor or microcomputer under test; and

comparison means for receiving machine codes from both said first storage means and said expected machine code storage means to compare said received machine codes and said expected machine code from said microprocessor or microcomputer under test,

wherein said first storage means is operable for storing all the machine code provided from the microprocessor or microcomputer under test and

said expected value storage means is operable for storing expected values of said all of the machine code to be provided from the microprocessor or microcomputer under test,

whereby proper or faulty functioning of the microprocessor or microcomputer under test is determined.

4. A semiconductor test system as recited in claim 3, wherein said comparison means is operable for comparing said machine codes provided from the microprocessor or microcomputer under test and said expected machine code every test cycle on all of the machine code signals.

5. A semiconductor test system as recited in claim 3, further comprising second storage means for storing said predetermined procedure in a form identical to internal machine code specific to said microprocessor or microcomputer under test and for directly supplying said predetermined procedure to said microprocessor or microcomputer under test.

6. A semiconductor test system as recited in claim 5, wherein said comparison means is operable for comparing said machine codes provided from the microprocessor or microcomputer under test and said expected machine code every test cycle on all of the machine code signals.

7. A semiconductor testing method for testing functions of a microprocessor or microcomputer comprising the steps of:

storing machine codes supplied from performance of said functions by said microprocessor or microcomputer under test, said microprocessor or microcomputer operating along a predetermined procedure;

storing expected machine codes to be supplied from performance of said functions by said microprocessor or microcomputer under test;

comparing said machine codes supplied from performance of said functions by said microprocessor or microcomputer under test with said expected machine codes supplied from said microprocessor or microcomputer under test, and

determining proper or faulty functioning of the microprocessor or microcomputer under test,

wherein said comparing step is performed every test cycle on all of the machine code signals provided from the microprocessor or microcomputer under test.

8. A semiconductor testing method as recited in claim 7, wherein said first mentioned storing step comprises storing all machine codes supplied from performance of said functions by said microprocessor or microcomputer under test, and said second mentioned storing step comprises storing expected values for all machine codes to be supplied from performance of said functions by said microprocessor or microcomputer under test.

9. A semiconductor testing method as recited in claim 8, comprising the further steps of storing said predetermined procedure in a form identical to internal machine code specific to said microprocessor or microcomputer under test and directly supplying said predetermined procedure to said microprocessor or microcomputer under test.