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Multipoint link data-transmission control system

  • US 4,888,728 A
  • Filed: 03/30/1987
  • Issued: 12/19/1989
  • Est. Priority Date: 03/29/1986
  • Status: Expired due to Fees
First Claim
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1. A multipoint link data-transmission control system having a master transmission device to which a master processor is connected, and a slave transmission device connected via a synchronous bus to said master transmission device, to which a plurality of slave processors are connected, said slave processors transmitting message data to said master transmission device, said slave transmission device comprising:

  • a receiving section comprising decoding means for decoding message data transmitted from said master transmission device via said synchronous bus;

    said receiving section further comprising;

    flag means for indicating whether said slave transmission device transmits or not to said master transmission device, in accordance with a decoded output from said decoding means, said flag means connected to said synchronous bus;

    a transmission section comprising transmission data storage means for storing a message data to be transmitted to said master transmission device;

    said transmission section further comprising,transmitting means for transmitting the message data stored in said transmission data storage means,transmission control means for transmitting message data from said transmission data storage means to said transmitting means in accordance with flag data representing the resetting of said flag means during the transmission of the message data from said transmission data storage means, and said transmission control means stopping operation of said transmitting means after detecting that the message data has been sent from said transmission data storage means, said transmission control means being connected to said flag means; and

    ,said plurality of slave processors transmit the message data from said transmission data storage means to said master transmission device in accordance with a corresponding time slot assigned to each of said plurality of slave processors.

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