TDMA terminal controller

• US 4,888,769 A
• Filed: 01/18/1989
• Issued: 12/19/1989
• Est. Priority Date: 12/06/1985
• Status: Expired due to Fees

• Current Assignee: TIW Systems, Inc. (General Dynamics Corporation)
• Original Assignee: TIW Systems, Inc. (General Dynamics Corporation)
• Inventors: Deal, Joseph H.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Marcelo, Melvin
• Application Number:
  US07/298,829
• Time in Patent Office: 335 Days
• Field of Search: 370/50, 370/75, 370/79, 370/80, 370/85, 370/94, 370/97, 370/104, 370/124, 370/120, 370/121, 375/8, 455/12
• US Class Current: 370/321
• CPC Class Codes: H04B 7/212 Time-division multiple access [TDMA]

Abstract

A TDMA terminal is disclosed having a plurality of terrestrial interface ports, and a plurality of modems for modulating preamble and port data onto a carrier and demodulating the received data transmitted via a satellite from the carrier wherein the interface ports and modems are fully connected over a common bus arrangement. The TDMA terminal controller defines the sequence of transmission (TX) and reception (RX) of information through these multiple ports and modems. The control sequencing selectively activates the ports and modems to accommodate current traffic requirements. This is achieved by presenting clock timing signals and port address signals repetitively to the ports during each transmission frame to couple the ports to the bus for transmit and receive information during the allocated burst intervals. This sequencing system adds or deletes bursts, for selectively defining the ports and modems to be coupled to the bus. clock intervals ("phases") are added to or deleted from the addressing sequence to modify the timing of the transmission frame; in this way the frame is centered relative to the transmission and receive aperture, in order that terminal the remains fully synchronized with the transmission of information.

Claims

1. A time division multiple access (TDMA) terminal comprising a plurality of terrestrial interface ports, a plurality of TDMA modulators and demodulators for modulating preamble and port data on a carrier and demodulating data from the carrier, the interface ports and the modulators and demodulators being fully interconnected over a common bus arrangement,

a TDMA terminal controller comprising means for sequencing the flow of said data to said modulators and demodulators over said common bus, and said sequencing means comprising means during each time frame for transmitting null addresses to said ports, disabling bus access to the interface ports and transmit/receive units included therein.

2. A terminal as claimed in claim 1 for communicating complete TDMA bursts including sub-bursts directed to said interface ports, said sequencing means comprising means for selectively activating each of said ports.

3. A terminal as claimed in claim 2 wherein said sequencing means selectively activate each of said ports separately for transmitting and for receiving.

4. A terminal as claimed in claim 2 wherein said sequencing means further comprise means for presenting clock timing signals and port address signals repetitively to said ports during each transmission frame to couple said ports to said bus.

5. A terminal as claimed in claim 2 wherein said sequencing means comprises means for generating separate transmit and receive lists of control phase signals, and means for controlling the time of generation of said phase signals by generating additional phase count signals.

6. A time division multiple access (TDMA) terminal comprising a plurality of terrestrial interface ports, a plurality of TDMA modulators and demodulators for modulating preamble and port data on multiple simultaneous carriers and demodulating data from multiple simultaneous carriers, the interface ports and the modulators and demodulators being fully interconnected over a common multiple phase bus arrangement,

and a TDMA terminal controller and said multiple phase bus comprising means for sequencing the flow of said multiple, independent data streams to said modulators and demodulators over said common multiple phase bus.

7. A terminal as claimed in claim 6 for communicating complete multiple simultaneous TDMA bursts to and from a plurality of distant TDMA terminals and demultiplexing data sub-bursts from the total received TDMA bursts and directing these sub-bursts to said interface ports, and sequencing means comprising means for selectively activating each of said ports and independently associating the various ports with the various modulators and demodulators for the transmission and reception of data.

8. A terminal as claimed in claim 7 wherein said sequencing means selectively activate each of said ports separately and independently, and associating a particular bus phase with the data passing between a particular modulator/demodulator and port for transmitting and for receiving.

9. A terminal as claimed in claim 7 wherein said sequencing means further comprise means for presenting the multiple phase clock timing signals and port address signals repetitively to said ports during each transmission frame to independently and simultaneously couple said multiple ports and modems to said multiple phase bus.

10. A terminal as claimed in claim 6 wherein said sequencing means comprises means during each time frame for transmitting multiple phase addressing and null addresses to said ports each of the null addresses being used for disabling bus access to the ports and the transmit/receive units for specific bus phases.

11. A terminal as claimed in claim 10 wherein said multiple phase sequencing mean comprises means for generating separate, simultaneous and independent transmit and receive control phase signals, and means for controlling the time of generation including the simultaneous generation of multiple said signals with a separate set of independent signals available for each bus phase.

12. A terminal as claimed in claim 11 wherein said sequencing means selectively activate each of said ports separately and independently, and associating a particular bus phase with the data passing between a particular modulator/demodulator and port for transmitting and for receiving.

13. A terminal as claimed in claim 10 for communicating complete multiple simultaneous TDMA bursts to and from a plurality of distant TDMA terminals and demultiplexing data sub-bursts from the total received TDMA bursts and directing these sub-bursts to said interface ports, and sequencing means comprising means for selectively activating each of said ports and independently associating the various ports with the various modulators and demodulators for the transmission and reception of data.

14. A terminal as claimed in claim 13 wherein said sequencing means selectively activate each of said ports separately and independently, and associating a particular bus phase with the data passing between a particular modulator/demodulator and port for transmitting and for receiving.

15. A terminal as claimed in claim 14 wherein said sequencing means further comprise means for presenting the multiple phase clock timing signals and port address signals repetitively to said ports during each transmission frame to independently and simultaneously couple said multiple ports and modems to said multiple phase bus.