Method of forming a high temperature stable ohmic contact to a III-V substrate

• US 4,889,831 A
• Filed: 11/30/1987
• Issued: 12/26/1989
• Est. Priority Date: 05/08/1987
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Shibatomi, Akihiro, Oshima, Toshio, Ishii, Kazuaki, Fujii, Toshio, Yokoyama, Naoki, Futatsugi, Toshiro
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US07/126,339
• Time in Patent Office: 757 Days
• Field of Search: 437/184, 437/187, 437/189, 437/192, 437/912, 437/133, 437/40, 437/41, 437/43, 437/176, 437/177, 437/31, 437/32, 437/33, 357/22 A, 357/15, 357/16, 357/30 A, 148/DIG. 10, 148/DIG. 11, 148/DIG. 65
• US Class Current: 438/508
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/66924 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: Y10S 148/01 Bipolar transistors-ion implantation
• CPC Class Codes: Y10S 148/065 Gp III-V generic compounds-processing

Abstract

An electrode structure of an electrode of a refractory metal or a silicide thereof on a layer of In_x Ga_1-x As (0<x<1) on a substrate of a III-V compound semiconductor is ohmic and is stable even at a high temperature, for example, 900° C. This high temperature stable ohmic electrode structure allows ion implantation into the substrate with the electrode as a mask followed by annealing to form a doped region in alignment with the edge of the electrode.

Claims

1. A process for manufacturing a semiconductor device, comprising the steps of:

preparing a substrate of a III-V compound semiconductor having a type of conductivity;

forming a layer of In_x Ga_1-x As on the substrate, wherein the layer has x greater than 0 and less than 1, wherein said layer has a type of conductivity the same as the type of conductivity of the substrate, and wherein the layer forms an ohmic contact with the substrate;

forming an electrode of a refractory metal or a silicide thereof on the In_x Ga_1-x As layer, wherein the electrode has an edge and forms an ohmic contact with the In_x Ga_1-x As layer;

patterning the In_x Ga_1-x As layer in alignment with the edge of the electrode with the electrode as a mask;

locally implanting an ion into a region of the substrate with the electrode as a mask, so as to have the ion-implanted region of the substrate be made in alignment with the edge of the electrode; and

heat annealing to activate the ion-implanted region of the substrate.

2. A process according to claim 1, further comprising a step of forming a buffer layer between the substrate and the In_x Ga_1-x As layer to match the lattices therebetween.

3. A process according to claim 1, wherein the III-V compound semiconductor is selected from the group consisting of GaAs, InP, AlGaAs, InGaAs, InAlP and InAlAs.

4. A process according to claim 1, wherein x of the In_x Ga_1-x As is a value between 0.5 and 1.0.

5. A process according to claim 4, wherein x of the In_x Ga_1-x As is 0.53.

6. A process according to claim 1, wherein the refractory metal is selected from the group of tungsten, molybdenum and tantalum.

7. A process according to claim 1, wherein the In_x Ga_1-x As layer is side etched slightly inward from the edge of the electrode.

8. A process according to claim 1, further comprising a step of forming an insulating film on the side walls of the electrode and the In_x Ga_1-x As layer after patterning thereof.

9. A process according to claim 1, wherein the heat annealing step is performed at a temperature equal to or more than 650°

C.