Phase locked loop having a fast lock current reduction and clamping circuit

• US 4,890,072 A
• Filed: 02/03/1988
• Issued: 12/26/1989
• Est. Priority Date: 02/03/1988
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Ecklund, Lawrence M., Espe, Roy H.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/151,870
• Time in Patent Office: 692 Days
• Field of Search: 331/10, 331/11, 331/17, 307/510, 307/511, 307/514, 307/516, 328/133, 328/134, 328/155, 455/260, 455/265
• US Class Current: 331/11
• CPC Class Codes: H03L 7/113 using frequency discriminator

Abstract

A circuit for use in a phase locked loop (PLL) which is responsive to the PLL being out of lock for providing fast lock current to drive the VCO of the PLL in the direction to acquire lock. The circuit includes a pair of controlled current sources responsive to selective control signals for either sourcing or sinking fast lock current at the output of the circuit that are utilized to produce an error control voltage at the loop filter to drive the VCO accordingly while a reducing circuit is responsive to the control voltage reaching a predetermined value as the VCO is driven toward one end or the other of its range for clamping the control voltage while reducing the fast lock current to a reduced value thereby limiting excessive charge build-up on the loop filter capacitor of the PLL. Thus, the circuit permits the VCO to acquire fast lock up by providing fast lock current thereto while clamping the range of the VCO and reducing the fast lock current as the VCO approaches either end of its range. Upon acquiring lock up, the controlled current sources are disabled.

Claims

1. A circuit responsive to control signals applied thereto for alternatively sourcing and sinking current at an output, comprising:

a first controlled current source responsive to selective ones of the control signals for sourcing a current of a predetermined magnitude to the output of the circuit;

a second controlled current source responsive to other selective ones of the control signals for sinking a current of a predetermined magnitude from the output of the circuit; and

reducing means for respectively reducing said currents of said first and second controlled current sources whenever the voltage potential at the output of the circuit becomes greater than a first predetermined value or less than a second predetermined value respectively.

6. The circuit of claim 1 further comprising a low pass filter of a phase locked loop to which the output of the circuit is connected thereto.

2. A circuit responsive to control signals applied thereto for alternatively sourcing and sinking current at an output, comprising:

a first controlled current source responsive to selective ones of the control signals for sourcing a current of a predetermined magnitude to the output of the circuit;

a second controlled current source responsive to other selective ones of the control signals for sinking a current of a predetermined magnitude from the output of the circuit; and

reducing means for respectively reducing said currents of said first and second controlled current sources whenever the voltage potential at the output of the circuit becomes greater than a first predetermined value or less than a second predetermined value respectively;

wherein said first controlled current source includes,

a. a first current mirror circuit having an input to which selective ones of the control signals are applied and an output;

b. a second current mirror circuit having an input coupled to said output of said first current mirror circuit and an output coupled to the output of the circuit for sourcing the current thereto; and

c. a first transistor having its collector-emitter conduction path coupled in parallel to said input of said first current mirror circuit which is responsive to a first reducing signal supplied from said reducing means to the base thereof for reducing the currents flowing in said first and second current mirror circuits.

3. The circuit of claim 2 wherein said second controlled current source includes:

a third current mirror circuit having an input to which said other selective ones of said control signals are applied, and an output coupled to the output of the circuit; and

a second transistor having its collector-emitter conduction path coupled in parallel to said input of said third current mirror circuit which is responsive to a second reducing signal supplied from said reducing means to the base thereof for reducing the currents flowing in said third current mirror circuit.

4. The circuit of claim 3 wherein said reducing means include:

a third transistor having a base, a collector and an emitter, said base being coupled to a terminal to which a reference potential is supplied, said emitter being coupled to the output of the circuit and said collector being coupled to said base of said first transistor;

a fourth transistor having a base, a collector and an emitter, said base being coupled to a terminal to which a reference potential is supplied, said emitter being coupled to the output of the circuit; and

a fourth current mirror circuit having an input coupled to said collector of said fourth transistor and an output coupled to said base of said second transistor.

5. The circuit of claim 4 wherein said bases of said third and fourth transistors are connected together to a terminal at which is supplied a single reference potential.

7. In a phase or quadrature locked loop including a low pass filter and means for generating quadrature beat notes whenever the phase locked loop is out of lock and circuit means for generating alternating control signals, the improvement comprising a circuit for providing fast lock pull up and pull down currents to the low pass filter when the phase locked loop is out of lock and for reducing such currents when the control voltage developed by the low pass filter becomes either greater than a first predetermined value or less than a second predetermined value, the circuit including:

a first controlled current source responsive to selective ones of the control signals for sourcing a current of a predetermined magnitude to the output of the circuit;

a second controlled current source responsive to other selective ones of the control signals for sinking a current of a predetermined magnitude from the output of the circuit; and

reducing means for respectively reducing said currents of said first and second controlled current sources whenever the voltage potential at the output of the circuit becomes greater than said first predetermined value or less than said second predetermined value respectively.

8. In a phase or quadrature locked loop including a low pass filter and means for generating quadrature beat notes whenever the phase locked loop is out of lock and circuit means for generating alternating control signals, the improvement comprising a circuit for providing fast lock pull up and pull down currents to the low pass filter when the phase locked loop is out of lock and for reducing such currents when the control voltage developed by the low pass filter becomes either greater than a first predetermined value or less than a second predetermined value, the circuit including:

a first controlled current source responsive to selective ones of the control signals for sourcing a current of a predetermined magnitude to the output of the circuit;

a second controlled current source responsive to other selective ones of the control signals for sinking a current of a predetermined magnitude from the output of the circuit; and

reducing means for respectively reducing said currents of said first and second controlled current sources whenever the voltage potential at the output of the circuit becomes greater than said first predetermined value or less than said second predetermined value respectively;

wherein said first controlled current source includes,

a. a first current mirror circuit having an input to which said selective ones of the control signals are applied and an output;

b. a second current mirror circuit having an input coupled to said output of said first current mirror circuit and an output coupled to the output of the circuit for sourcing the current thereto; and

c. a first transistor having its collector-emitter conduction path coupled in parallel to said input of said first current mirror circuit which is responsive to a first reducing signal supplied from said reducing means to the base thereof for reducing the currents flowing in said first and second current mirror circuits.

9. The circuit of claim 8 wherein said second controlled current source includes:

a third current mirror circuit having an input to which said other selective ones of said control signals are applied, and an output coupled to the output of the circuit; and

a second transistor having its collector-emitter conduction path coupled in parallel to said input of said third current mirror circuit which is responsive to a second reducing signal supplied from said reducing means to the base thereof for reducing the current flowing in said third current mirror circuit.

10. The circuit of claim 9 wherein said reducing means includes:

a third transistor having a base, a collector and an emitter, said base being coupled to a terminal to which a reference potential is supplied, said emitter being coupled to the output of the circuit and said collector being coupled to said base of said first transistor;

a fourth transistor having a base, a collector and an emitter, said base being coupled to said terminal, said emitter being coupled to the output of the circuit; and

a fifth transistor having a base, first and second collectors and an emitter, said base being coupled both to said first collector and said collector of said fourth transistor, said second collector being coupled to said base of said second transistor and said emitter being coupled to a power supply conductor.

11. A receiver for receiving AM stereophonic signals and including a phase locked loop (PLL), the PLL having a low pass filter and means for generating quadrature beat notes whenever the phase locked loop is out of lock and circuit means for generating alternating control signals, the improvement comprising a circuit for providing fast lock pull up and pull down currents to the low pass filter when the phase locked loop is out of lock and for reducing such currents when the control voltage developed by the low pass filter becomes either greater than a first predetermined value or less than a second predetermined value, the circuit including:

a first controlled current source responsive to selective ones of the control signals for sourcing a current of a predetermined magnitude to the output of the circuit;

a second controlled current source responsive to other selective ones of the control signals for sinking a current of a predetermined magnitude from the output of the circuit; and

reducing means for respectively reducing said currents of said first and second controlled current sources when the voltage potential at the output of the circuit becomes greater than said first predetermined value or less than said second predetermined value respectively.

12. A receiver for receiving AM stereophonic signals and including a phase locked loop (PLL), the PLL having a low pass filter and means for generating quadrature beat notes whenever the phase locked loop is out of lock and circuit means for generating alternating control signals, the improvement comprising a circuit for providing fast lock pull up and pull down currents to the low pass filter when the phase locked loop is out of lock and for reducing such currents when the control voltage developed by the low pass filter becomes either greater than a first predetermined value or less than a second predetermined value, the circuit including:

a first controlled current source responsive to selective ones of the control signals for sourcing a current of a predetermined magnitude to the output of the circuit;

a second controlled current source responsive to other selective ones of the control signals for sinking a current of a predetermined magnitude from the output of the circuit; and

reducing means for respectively reducing said currents of said first and second controlled current sources when the voltage potential at the output of the circuit becomes greater than said first predetermined value or less than said second predetermined value respectively;

wherein said first controlled current source includes,

a. a first current mirror circuit having an input to which said selective ones of the control signals are applied and an output;

b. a second current mirror circuit having an input coupled to said output of said first current mirror circuit and an output coupled to the output of the circuit for sourcing the current thereto; and

c. a first transistor having its collector-emitter conduction path coupled in parallel to said input of said first current mirror circuit which is responsive to a first reducing signal supplied from said reducing means to the base thereof for reducing the currents flowing in said first and second current mirror circuits.

13. The circuit of claim 12 wherein said second controlled current source includes:

a third current mirror circuit having an input to which said other selective ones of said control signals are applied, and an output coupled to the output of the circuit; and

a second transistor having its collector-emitter conduction path coupled in parallel to said input of said third current mirror circuit which is responsive to a second reducing signal supplied from said reducing means to the base thereof for reducing the currents flowing in said third current mirror circuit.

14. The circuit of claim 13 wherein said reducing means includes:

a third transistor having a base, a collector and an emitter, said base being coupled to a terminal to which a reference potential is supplied, said emitter being coupled to the output of the circuit and said collector being coupled to said base of said first transistor;

a fourth transistor having a base, a collector and an emitter, said base being coupled to said terminal, said emitter being coupled to the output of the circuit; and

a fifth transistor having a base, first and second collectors and an emitter, said base being coupled both to said first collector and said collector of said fourth transistor, said second collector being coupled to said base of said second transistor and said emitter being coupled to a power supply conductor.