Apparatus for substantially syncronizing the timing subsystems of the physical modules of a local area network

• US 4,890,222 A
• Filed: 06/24/1987
• Issued: 12/26/1989
• Est. Priority Date: 12/17/1984
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Kirk, David L.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US07/065,974
• Time in Patent Office: 916 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 370/85, 370/63, 375/106, 340/825.2
• US Class Current: 713/400
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: H04B 3/544 Setting up communications; Call and signalling arrangements
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

A local area network has a plurality of modules, each module having a corresponding timing subsystem. Each timing subsystem includes a clock unit for generating clock pulses, and an a.c. power source. Each timing subsystem is capable of having the timing information generated by each timing subsystem substantially synchronized to the timing information generated by a timing subsystem designated as a master timing subsystem. Each timing subsystem includes a first element, adapted to receive clock pulses and an a.c. reference signal generated from an a.c. power source, which generates timing information from the clock pulses or the a.c. reference signal in response to commands from the module. A register element stores the timing information generated. A second element updates the timing information stored in the register element with timing information included in a timing frame in response to a predetermined command from the module. The timing frame is periodically transmitted by the timing subsystem designated as the master timing subsystem, to each timing subsystem of each module. The timing frame includes timing information generated by the master timing subsystem, thereby resulting in having the timing information of each timing subsystem of each module substantially the same as the timing information of the master timing subsystem.

Claims

1. In a local area network having a plurality of modules, each module being capable of communicating with every other module over a network bus, and wherein each module includes a module central processor unit (MCPU), and an associated clock unit operatively connected to the MCPU providing clock pulses thereto, and wherein each module is adapted to be powered by a source of a.c. power having a given frequency, and further wherein each module includes a timing subsystem capable of being substantially synchronized to a master timing subsystem, said timing subsystem comprising:

(a) first means, adapted to receive said clock pulses, an a.c. reference timing signal generated from said source of a.c. power, commands from said MCPU, and a timing frame, for generating timing information from said clock pulses or said a.c. reference timing signal in response to said commands received from said MCPU, thereby resulting in the timing information synchronized to said clock pulses or to said a.c. reference timing signal;

(b) register means, coupled to said first means to said MCPU, for storing said timing information, thereby making said timing information available to the MCPU; and

(c) second means, coupled to said register means and said first means, for updating the timing information stored in said register means with the timing information included in said timing frame in response to a predetermined command from said MCPU, the timing frame being periodically transmitted by the timing subsystem designated as the master timing subsystem to each timing subsystem of each module via the network bus, the timing frame including the timing information generated by the master timing subsystem, thereby resulting in having the timing information of each timing subsystem of each module substantially synchronized to the timing information of the master timing subsystem.