Paged memory management unit which evaluates access permissions when creating translator

• US 4,890,223 A
• Filed: 07/21/1988
• Issued: 12/26/1989
• Est. Priority Date: 01/15/1986
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Moyer, William C., Zolnowsky, John, Cruess, Michael W.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): KULIK, PAUL V
• Application Number:
  US07/223,731
• Time in Patent Office: 523 Days
• Field of Search: 364/200, 364/900
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/1475 in a virtual system, e.g. with translation means

Abstract

A paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU assembling each of the logical addresses and the corresponding physical address into a respective translator. In general, the PMMU includes: a cache having a plurality of storage locations for storing the translators, each of the storage locations including a write protect indicator and a read protect indicator adapted to be selectively set; translation control logic for storing an assembled translator in a selected one of the storage locations, the translation control logic setting the write protect indicator of the one storage location in response to a write protect signal associated with the descriptor used to assemble the translator and the read protect indicator of the one storage location in response to a read protect signal associated with that descriptor; and access control logic for preventing the translator from being used to translate the logical address in support of a write operation if the write protect indicator of the one storage location is set or in support of a read operation if the read protect indicator of the one storage location is set. In the preferred form, the logical address has an access privilege level associated therewith and the descriptor includes a selected write access privilege level and a selected read access privilege level, the translation control logic setting the write protect indicator of the one storage location if the access privilege level associated with the logical address is logically less than the write access privilege level and the read protect indicator of the one storage location if the access privilege level associated with the logical address is logically less than the read access privilege level.

Claims

1. In a page memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU receiving each of said logical addresses and the corresponding physical address from the memory, said PMMU including:

a cache having a plurality of storage locations for storing said translators, each of said storage locations including a write protect indicator and a read protect indicator adapted to be selectively set;

control means for assembling each of said logical addresses and the corresponding physical address into a respective translator and controlling the storing of each translator in a selected one of said storage locations, the control means setting the write protect indicator of said one storage location in response to a write protect signal associated with the descriptor used to assemble said translator and setting the read protect indicator of said one storage location in response to a read protect signal associated with the descriptor used to assemble said translator; and

access control means for preventing said translator from being used to translate said logical address in support of a write operation when the write protect indicator of said one storage location is set and for preventing said translator from being used to translate said logical address in support of a read operation when the read protect indicator of said one storage location is set;

wherein said logical address has an access privilege level associated therewith and said descriptor includes a selected write access privilege level and a selected read access privilege level, said control means;

setting said write protect indicator of said one storage location to prevent said translator from being used in support of a write operation when the access privilege level associated with said logical address is logically less than said write access privilege of said descriptor; and

setting said read protect indicator of said one storage location to prevent said translator from being used in support of a read operation when the access privilege level associated with said logical address is logically less then said read access privilege level of said descriptor;

wherein said translator is assembled by the control means and stored in said one storage location even when the access privilege associated with said logical address is not logically less than said write a read access privilege levels of said descriptor, but is not allowed by the access control means to be used in support of a write operation, even when said descriptor used to assemble said translator does not have said write protect signal associated therewith, unless the access privilege associated with said logical address is at least equal to said write access privilege or said descriptor, or is not allowed by the access control means to be used in support of a read operation, even when said descriptor used to assemble said translator does not have said read protect signal associated therewith, unless the access privilege level associated with said logical address is at least equal to said read access privilege level of said descriptor.

2. In the PMMU of claim 1, the further improvement wherein said write protect signal comprises a portion of said descriptor.

3. In the PMMU of claim 2, the further improvement wherein said read protect signal comprises a portion of said descriptor.

4. In the PMMU of claim 1, the further improvement wherein said read protect signal comprises a portion of said descriptor.

5. In the PMMU of claim 1, wherein the translation tables are comprised of one or more descriptor tables each comprised of a plurality of said descriptors, and a plurality of pointer tables each comprised of one or more table pointers to respective ones of said descriptor tables, the PMMU translating said logical address into said physical address by first combining a first portion of said logical address and a selected root pointer to access a first one of said pointer tables to obtain therefrom a table pointer to a selected one of said descriptor tables and then combining a second portion of said logical address and said table pointer to access said selected descriptor table to obtain therefrom said physical address, the improvement wherein said write protect signal comprises a portion of said table pointer and is associated with all descriptors comprising said selected descriptor table.

6. In the PMMU of claim 5, the further improvement wherein said read protect signal comprises a portion of said table pointer and is associated with all descriptors comprising said selected descriptor table.

7. In a paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU receiving each of said logical addresses and the corresponding physical address from the memory, said PMMU including:

a cache having a plurality of storage locations for storing said translators, each of said storage locations including a write protect indicator adapted to be selectively set;

control means for assembling each of said logical addresses and the corresponding physical address into a respective translator and controlling the storing of an assembled translator in a selected one of said storage locations, the control means setting the write protect indicator of said one storage location in response to a write protect signal associated with the descriptor used to assemble said translator; and

access control means for preventing said translator from being used to translate said logical address in support of a write operation when the write protect indicator of said one storage location is set;

wherein said logical address has an access privilege level associated therewith and said descriptor includes a selected write access privilege level, said control means setting said write protect indicator of said one storage location to prevent said translator from being used in support of a write operation when the access privilege level associated with said logical address is logically less than said write access privilege level of said descriptor, wherein said translator is assembled by the control means and stored in said one storage location even when the access privilege level associated with said logical address is not logically less than said write access privilege level of said descriptor, but is not allowed by the access control means to be used in support of a write operation, even when said descriptor used to assemble said translator does not have said write protect signal associated therewith, unless the access privilege level associated with said logical address is at least equal to said write access privilege level of said descriptor.

8. In the PMMU of claim 7 wherein:

each of said storage locations also includes a read protect indicator adapted to be selectively set;

the control means set the read protect indicator of said one storage location in response to a read protect signal associated with the descriptor used in the assembly of said translator; and

the access control means prevent said translator from being used to translate said logical address in support of a read operation if the read protect indicator of said one storage location is set;

the further improvement wherein said descriptor also includes a selected read access privilege level, said control means setting said read protect indicator of said one storage location if the access privilege level associated with said logical address is logically less than said read access privilege level.

9. In the PMMU of claim 8, the further improvement wherein said write protect signal comprises a portion of said descriptor.

10. In the PMMU of claim 9, the further improvement wherein said read protect signal comprises a portion of said descriptor.

11. In the PMMU of claim 8, wherein the translation tables are comprised of one or more descriptor tables each comprised of a plurality of said descriptors, and a plurality of pointer tables each comprised of one or more table pointers to respective ones of said descriptor tables, the PMMU translating said logical address into said physical address by first combining a first portion of said logical address and a selected root pointer to access a first one of said pointer tables to obtain therefrom a table pointer to a selected one of said descriptor tables and then combining a second portion of said logical address and said table pointer to access said selected descriptor table to obtain therefrom said physical address, the improvement wherein said write protect signal comprises a portion of said table pointer and is associated with all descriptors comprising said selected descriptor table.

12. In the PMMU of claim 11, the further improvement wherein said read protect signal comprises a portion of said table pointer and is associated with all descriptors comprising said selected descriptor table.

13. In the PMMU of claim 7, the further improvement wherein said write protect signal comprises a portion of said descriptor.

14. In the PMMU of claim 7 wherein the translation tables are comprised of one or more descriptor tables each comprised of a plurality of said descriptions, and a plurality of pointer tables each comprised of one or more table pointers to respective ones of said descriptor tables, the PMMU translating said logical address into said physical address by first combining a first portion of said logical address and a selected root pointer to access a first one of said pointer tables to obtain therefrom a table pointer to a selected one of said descriptor tables and then combining a second portion of said logical address and said table pointer to access said selected descriptor table to obtain therefrom said physical address, the improvement wherein said write protect signal comprises a portion of said table pointer and is associated with all descriptors comprising said selected descriptor table.

15. In a paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU receiving each of said logical addresses and the corresponding physical address into a respective translator, said PMMU including:

said

a cache having a plurality of storage locations for storing said translators, each of said storage locations including a read protect indicator adapted to be selectively set;

control means for assembling each of said addresses and the corresponding physical address into a respective translator and controlling the storing of each translator in a selected one of said storage locations, the control means setting the read protect indicator of said one storage location in response to a read protect signal associated with the descriptor used to assemble said translator; and

access control means for preventing said translator from being used to translate said logical address in support of a read operation when the read protect indicator of said one storage location is set;

wherein said logical address has an access privilege level associated therewith and said descriptor includes a selected read access privilege level, said control means setting said read protect indicator of said one storage location to prevent said translator from being used in support of a read operation when the access privilege level associated with said logical address is logically less than said read access privilege level of said descriptor, wherein said translator is assembled by the control means and stored in said on®

storage location even when the access privilege level associated with said logical address is not logically less than said read access privilege level of said descriptor, but is not allowed by the access control means to be used in support of a read operation, even when said descriptor used to assemble said translator does not have said read protect signal associated therewith, unless the access privilege level associated with said logical address is at least equal to said read access privilege level of said descriptor.

16. In the PMMU of claim 15 wherein:

each of said storage locations also includes a write protect indicator adapted to be selectively set;

the control means set the write protect indicator of said one storage location in response to a write protect signal associated with the descriptor used in the assembly of said translator; and

the access control means prevent said translator from being used to translate said logical address in support of a write operation if the write protect indicator of said one storage location is set;

the further improvement wherein said descriptor also includes a selected write access privilege level, said control means setting said write protect indicator of said one storage location if the access privilege level associated with said logical address is logically less than said write access privilege level.

17. In the PMMU of claim 16, the further improvement wherein said write protect signal comprises a portion of said descriptor.

18. In the PMMU of claim 17, the further improvement wherein said read protect signal comprises a portion of said descriptor.

19. In the PMMU of claim 16, wherein the translation tables are comprised of one or more descriptor tables each comprised of a plurality of said descriptors, and a plurality of pointer tables each comprised of one or more table pointers to respective ones of said descriptor tables, the PMMU translating said logical address into said physical address by first combining a first portion of said logical address and a selected root pointer to access a first one of said pointer tables to obtain therefrom a table pointer to a selected one of said descriptor tables and then combining a second portion of said logical address and said table pointer to access said selected descriptor table to obtain therefrom said physical address, the improvement wherein said write protect signal comprises a portion of said table pointer and is associated with all descriptors comprising said selected descriptor table.

20. In the PMMU of claim 19, the further improvement wherein said read protect signal comprises a portion of said table pointer and is associated with all descriptors comprising said selected descriptor table.

21. In the PMMU of claim 15, the further improvement wherein said write protect signal comprises a portion of said descriptor.

22. In the PMMU of claim 15 wherein the translation tables are comprised of one or more descriptor tables each comprised of a plurality of said descriptors, and a plurality of pointer tables each comprised of one or more table pointers to respective ones of said descriptor tables, the PMMU translating said logical address into said physical address by first combining a first portion of said logical address and a selected root pointer to access a first one of said pointer tables to obtain therefrom a table pointer to a selected one of said descriptor tables and then combining a second portion of said logical address and said table pointer to access said selected descriptor table to obtain therefrom said physical address, the improvement wherein said write protect signal comprises a portion of said table pointer and is associated with all descriptors comprising said selected descriptor table.