Method for physical VLSI-chip design

• US 4,890,238 A
• Filed: 12/15/1987
• Issued: 12/26/1989
• Est. Priority Date: 12/17/1986
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Klein, Klaus, Schulz, Uwe, Zuehlke, Rainer, Schettler, Helmut, Wagner, Otto M., Pollmann, Kurt
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): TRANS, VINCENT N
• Application Number:
  US07/133,402
• Time in Patent Office: 742 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/300
• US Class Current: 716/124
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

For the physical design of a very large scale integration (VSLI) chip, a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology, the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus, the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip need no extra space for global wiring and the partitions are immediately attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.

Claims

1. A method for the physical design of a chip, said chip being divided into several partitions and containing a high number of electrical circuits wherein connections exist between partitions, which method includes the steps of

logically dividing into partitions the circuits to be placed on said chip,

determining space requirements of said partitions and placing said partitions onto different areas of said chip,

determining logic as well as crossing, ending and emerging connection lines within a given partition by treating connection lines within said given partition in the same way as circuits therein, and repeating this step sequentially for adjacent partitions until all partitions have been processed, at least some of said processed partitions having circuit densities that differ from others of said processed partitions,

shaping the processed partitions into various shapes so that they fit to each other without leaving space in between the neighboring edges of said adjacent partitions,

determining interconnect contact points at the boundaries of said partitions by starting in one specific area of the chip and propagating step-by-step in a given direction to form exit information and contact areas of one of said partitions as the input information or placement respectively for the successive adjacent partition or partitions respectively, and

abutting on said chip the appropriately shaped partitions so that each of said partitions is positioned seamlessly to another of said partitions.

2. A method for the physical design of a semiconductor chip, said chip being divided into several partitions and containing a high number of electrical circuits wherein connections exist between said partitions, which method includes the steps of

logically dividing in several partitions all circuits to be contained on the chip,

establishing a floor plan that reflects space requirements as well as locations of said partitions,

said partitions being completely processed independently and in parallel by treating the interconnection lines that cross, emerge or end in a given partition the same as the internal circuits,

physically defining said partitions so that at least one of said partitions have a shape that is different from that of the other of said partitions, such that on the spatial area of the chip said partitions fit together at adjacent edges without leaving space in between, and such that associated inter-connect-points match each other, and

determining interconnect contact points at the boundaries of said partitions by starting in one specific area of said chip and propagating step-by-step in a given direction to form exit information and contact areas of one of said partitions as the input information or placement respectively for the successive adjacent partition or partitions respectively.

3. A method as set forth in claim 2 further including

adjusting and varying the density or porosity respectively of partitions or regions.

4. A method as set forth in claim 2 further including

forming the density of crossing interconnection lines in the middle of a region/partition higher than in the outer areas of that respective region/partition and forming the density of circuits in the outer areas of that respective region/partition higher than in the middle thereof.

5. A method as set forth in claim 2 further including

establishing transfer books with logical functions, provided by electrical circuits, as well as transfer books with non-logical functions, provided by connection and transfer wires, both sort of books being disposed adjacent at the perimeter of its respective partition and defining the boundary interconnect-contact areas.

6. A method as set forth in claim 5 further including

assigning formal blockage circuits to blockage areas, said blockage circuits having formal functions, and existing during processing for design purposes and being removable in the final design stage and final chip data.