High density integrated circuit analog signal recording and playback system

• US 4,890,259 A
• Filed: 07/13/1988
• Issued: 12/26/1989
• Est. Priority Date: 07/13/1988
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Information Storage Devices, Inc. (Winbond Electronics Corporation)
• Inventors: Simko, Richard T.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/218,634
• Time in Patent Office: 531 Days
• Field of Search: 365/45, 365/185, 365/189, 365/189.01, 365/189.07, 360/32, 360/39
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence

Abstract

The present invention is a high density integrated circuit analog signal recording and playback system. The recording and playback system is based upon an array storing analog signals. The array has rows and columns of non-volatile memory cells to store the signal information. Analog column read/write circuitry is used to both store the analog information and retrieve it on a real time basis, using interleaving of analog information on a plurality of sample/hold circuits prior to storage in the array to increase throughput.

Claims

1. A memory array for storing analog information comprising:

a plurality of rows and columns of electrically erasable programmable floating gate non-volatile memory cells each adapted for storing an analog signal;

column read/write circuitry coupled to the columns of said memory array for reading the analog signals stored in said memory, and for writing the analog signals into the array,

including means for iteratively charging a column of electrically erasable programmable read only memory cells by applying an interative series of write pulses to the selected cell, said write pulses having a predetermined voltage starting from a low voltage and increasing in voltage with time, whereby charging resolution is improved, thereby intelligently adjusting the charge and consequently adjusting the conductivity of a memory cell in direct relation to the voltage of the input signal to be stored;

first and second plurality of sample/hold circuits;

first transfer means coupled to the column read/write circuitry for storing analog input signals on one of said first and second plurality of sample/hold circuits;

second transfer means coupled to said column read/write circuitry for transferring said analog input signals from said first sample/hold circuit to said array while analog signals are being stored on said second sample/hold circuit; and

switching means coupled to said first and second transfer means for switching said analog input signals from one of said pluralities of sample/hold circuits to the other for storage when the storage capacity of said first plurality of sample/hold circuits is reached.

2. The memory array of claim 1 wherein said read circuitry includes a means for measuring the conductivity of a memory cell as an indication of the voltage of the input signal stored in said cell.

3. The memory array of claim 1 wherein said column read/write circuitry includes a means for measuring the conductivity of a memory cell as an indication of the voltage of the input signal stored in said cell.

4. Apparatus for storing analog information comprising:

a memory array comprising a plurality of rows and columns of floating gate non-volatile memory cells, each adapted for storing an analog signal;

a first and second plurality of sample/hold circuits;

first transfer means coupled to said read/write circuitry for storing analog input signals on one of said first and second plurality of sample/hold circuits;

switching means coupled to said transfer means for switching said analog input signals from one of said pluralities of sample/hold circuits to the other for storage when the storage capacity of said first plurality of sample/hold circuits is reached;

second transfer means coupled to said read/write circuitry for transferring said analog input signals from said first sample/hold circuit to said array while analog signals are being stored on said second sample/hold circuit;

write circuitry means coupled to said rows and columns of said memory array for selecting each individual cell and for storing a predetermined analog signal on its floating gate, said write circuitry including means for applying an interative series of write pulses to the selected cell, said write pulses having a predetermined voltage starting from a low voltage and increasing in voltage with time, whereby charging resolution is improved;

read circuitry means coupled to said rows and columns of said memory array for detecting the analog signal level on each individual cell and for outputting said analog signal level; and

control means coupled to said read and write circuitry means operating to cycle reading and writing through the individual cells in said memory array.

5. The apparatus of claim 4 wherein said write circuitry includes means for stopping the application of said write pulses to each cell of said plurality of cells when the charge on said cell is representative of said predetermined analog signal, or after a predetermined number of pulses have been applied, whichever is first to occur.

6. The apparatus of claim 4 wherein the range of voltages used for said senses of write pulses covers the range of normal charging voltages for said plurality of memory cells.

7. The apparatus of claim 6 wherein the low starting voltage is selected to be at the lower end of the normal charging voltage range for the cells of said plurality of memory cells.

8. The apparatus of claim 4 wherein said write circuitry means for applying said iterative series of write pulses draws sufficiently low current which can be supplied by a high voltage generator fabricated on the same chip as said array.

9. Apparatus for storing analog information comprising:

a memory array comprising a plurality of rows and columns of floating gate non-volatile memory cells, each adapted for storing an analog signal;

write circuitry means coupled to said rows and columns of said memory array for selecting each individual cell and for storing a predetermined analog signal on its floating gate, said write circuitry including means for applying an iterative series of write pulses to the selected cell, said write pulses having a predetermined voltage starting from a low voltage and increasing in voltage with time, whereby charging resolution is improved;

comparator means for iteratively comparing the relationship of the charge stored in said selected cell to the analog signal being stored, said comparator means being coupled to said means for applying said iterative series of write pulses, said comparator means causing the ceasation of said write pulses when the stored charge correctly relates to said analog signal;

read circuitry means coupled to said rows and columns of said memory array for detecting the analog signal level on each individual cell and for outputting said analog signal level; and

control means coupled to said read and write circuitry means operating to cycle reading and writing through the individual cells in said memory array.

10. The apparatus of claim 9 wherein said write circuitry means for applying said iterative series of write pulses draws sufficiently low current which can be supplied by a high voltage generator facricated on the same chip as said array.