Trilayer microlithographic process using a silicon-based resist as the middle layer
First Claim
1. A process for applying a pattern to a workpiece used in fabricating an integrated circuit, comprising the steps of:
- depositing a thick organic layer on a surface of the workpiece;
depositing a second layer containing an at least partially silicon-based polymer on the thick organic layer;
depositing an organic photoresist resolution layer on the second layer;
projecting a pattern image onto the resolution layer with a light source to which the resolution layer is sensitive;
developing the resolution layer to leave patterned orifices therethrough and to expose patterned areas of the outer surface of the second layer;
exposing the resolution layer and the patterned areas of the second layer to light to which the second layer is sensitive but which will be strongly absorbed by the resolution layer;
developing the second layer to create orifices therein extending from the patterned areas of the outer surface of the second layer to corresponding patterned areas on the outer surface of the thick organic layer; and
differentially etching exposed portions of the thick organic layer much faster than the second layer until the surface of the workpiece is reached.
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Abstract
A method for patterning an integrated circuit workpiece (10) includes forming a first layer (16) of organic material on the workpiece surface to a depth sufficient to allow a substantially planar outer surface (36) thereof. A second, polysilane-based resist layer (22) is spin-deposited on the first layer (16). A third resolution layer (24) is deposited on the second layer (22). The resolution layer (24) is selectively exposed and developed using standard techniques. The pattern in the resolution layer (24) is transferred to the polysilane layer (22) by either using exposure to deep ultraviolet or by a fluorine-base RIE etch. This is followed by an oxygen-based RIE etch to transfer the pattern to the surface (18) of the workpiece (10).
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Citations
13 Claims
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1. A process for applying a pattern to a workpiece used in fabricating an integrated circuit, comprising the steps of:
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depositing a thick organic layer on a surface of the workpiece; depositing a second layer containing an at least partially silicon-based polymer on the thick organic layer; depositing an organic photoresist resolution layer on the second layer; projecting a pattern image onto the resolution layer with a light source to which the resolution layer is sensitive; developing the resolution layer to leave patterned orifices therethrough and to expose patterned areas of the outer surface of the second layer; exposing the resolution layer and the patterned areas of the second layer to light to which the second layer is sensitive but which will be strongly absorbed by the resolution layer; developing the second layer to create orifices therein extending from the patterned areas of the outer surface of the second layer to corresponding patterned areas on the outer surface of the thick organic layer; and differentially etching exposed portions of the thick organic layer much faster than the second layer until the surface of the workpiece is reached. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification