Semiconductor packaging with ground plane conductor arrangement

• US 4,891,686 A
• Filed: 04/08/1988
• Issued: 01/02/1990
• Est. Priority Date: 04/08/1988
• Status: Expired due to Term

• Current Assignee: LFUS DEI, Inc. (Littelfuse Incorporated)
• Original Assignee: LFUS DEI, Inc. (Littelfuse Incorporated)
• Inventors: Krausse, George J. III
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US07/179,489
• Time in Patent Office: 634 Days
• Field of Search: 357/68, 357/65, 357/81, 357/22, 357/79, 357/74, 357/80, 333/12, 333/246, 361/400
• US Class Current: 174/252
• CPC Class Codes: H01L 2023/405 heatsink to package
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/854 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 23/4006 with bolts or screws
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Packaging techniques are described which provide electrical, thermal, and mechanical advantages. A low-profile semiconductor package is described in which the leads are flat and are present in the same plane. The leads are arranged and positioned in order to eliminate inductance. A semiconductor die is secured to a ceramic substrate, and a plurality of bond wires are secured between the pads on the die and the leads of the package.

Claims

1. A high power MOSFET semiconductor package comprising:

(a) a ceramic substrate having a planar upper surface and opposite side edges;

(b) a MOSFET semiconductor die secured to said upper surface of said ceramic substrate;

said die including gate, source and drain areas and having connection pads on said gate, source and drain areas;

(c) a gate signal carrying conductor electrically connected to said connection pad on said gate area;

(d) a drain signal carrying conductor electrically connected to said connection pad on said drain area;

(e) ground plane conductors disposed one each side, and separated from, and parallel to each of said signal carrying conductors;

wherein each said ground plane conductor is electrically connected to said connection pad on said source area;

wherein said ground plane conductors are disposed in the same plane as said signal carrying conductors.

2. A semiconductor package in accordance with claim 1, wherein said ceramic substrate comprises beryllium oxide.

3. A semiconductor package in accordance with claim 1, wherein there are two of said ground plane conductors which project from one side edge of said substrate and another two of said ground plane conductors project from the opposite side edge of said substrate.

4. A semiconductor package in accordance with claim 1, wherein each said conductor includes a stress relief bend.

5. A semiconductor package in accordance with claim 1, wherein each said conductor is copper.

6. A semiconductor package in accordance with claim 1, wherein each said ground plane conductor includes a metalization pad disposed on said ceramic substrate.

7. A semiconductor package in accordance with claim 6, wherein said gate signal carrying conductor and said drain signal carrying conductor project outwardly from opposite side edges of said substrate;

wherein there are four said ground plane conductors;

wherein two of said ground plane conductors are disposed on opposite sides of and spaced from said gate signal carrying conductor an equal distance, and wherein the other two of said ground plane conductors are disposed on opposite sides of and spaced from said drain signal carrying conductor an equal distance.

8. A semiconductor package in accordance with claim 1, wherein said gate signal carrying conductor and said drain signal carrying conductor comprise planar conductive strips;

wherein said gate signal carrying conductor and said drain signal carrying conductor project outwardly from opposite side edges of said substrate in the same plane;

wherein there are four said ground plane conductors;

wherein two of said ground plane conductors are disposed on opposite sides of and spaced from said gate signal carrying conductor an equal distance, and wherein the other two of said ground plane conductors are disposed on opposite sides of and spaced from said drain signal carrying conductor an equal distance.

9. A semiconductor package in accordance with claim 8, wherein each of said conductors is copper.

10. A semiconductor package in accordance with claim 1, wherein said ground plane conductors are terminated on a single connection pad on said source area.

11. A semiconductor package in accordance with claim 6, further comprising first, second, third and fourth sets of multiple bond wires each having first and second ends;

wherein said first ends of said first and second sets of bond wires are connected, respectively, to said ground plane conductor metalization pads which are adjacent to said gate signal carrying conductor;

wherein said first ends of said third and fourth sets of bond wires are connected, respectively, to said ground plane conductor metalization pads which are adjacent to said drain signal carrying conductor; and

wherein said second ends of said first, second, third and fourth sets of bond wires converge toward each other and are connected to said connection pad on said source area.

12. A semiconductor package in accordance with claim 1, wherein all said conductors are non-ferrous, non-magnetic materials.

13. A circuitry package comprising:

(a) a power MOSFET semiconductor package in accordance with claim 1;

(b) a printed circuit board;

(c) a heat sink;

wherein said semiconductor package is positioned on said heat sink in a manner such that said ceramic substrate is in thermal contact with said heat sink;

wherein said conductors are operably connected to said printed circuit board; and

wherein said semiconductor package is secured to said heat sink.

14. A circuitry package in accordance with claim 13, wherein each said ground plane conductor includes a metalization pad disposed on said ceramic substrate;

and said gate signal carrying conductor and said drain signal carrying conductor project outwardly from opposite side edges of said substrate;

wherein there are four said ground plane conductors;

wherein two of said ground plane conductors are disposed on opposite sides of and spaced from said gate signal carrying conductor an equal distance, and wherein the other two of said ground plane conductors are disposed on opposite sides of and spaced from said drain signal carrying conductor an equal distance.

15. A circuitry package in accordance with claim 14, wherein all said conductors are non-ferrous, non-magnetic materials;

wherein each said conductor includes a stress relief bend; and

wherein said ceramic substrate includes a bottom surface which is polished to facilitate thermal contact with said heat sink.